High voltage semiconductor devices and methods of making the devices

• US 10,290,732 B2
• Filed: 12/18/2017
• Issued: 05/14/2019
• Est. Priority Date: 02/11/2015
• Status: Active Grant

• Current Assignee: Monolith Semiconductor, Inc. (Littelfuse Incorporated)
• Original Assignee: Monolith Semiconductor, Inc. (Littelfuse Incorporated)
• Inventors: Matocha, Kevin, Chatty, Kiran, Banerjee, Sujit
• Primary Examiner(s): Schoenholtz, J. E.
• Application Number:
  US15/844,766
• Publication Number:
  US 20180122933A1
• Time in Patent Office: 512 Days
• Field of Search: None
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0485 Ohmic electrodes
• CPC Class Codes: H01L 21/0495 Schottky electrodes
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

Claims

1. A multi-cell MOSFET device comprising:

an n-type drift layer on an n-type substrate;

a plurality of MOSFET cells, each of the MOSFET cells comprising;

first and second p-type well regions in spaced relation on the n-type drift layer;

an n-type JFET region on the n-type drift layer between the first and second p-type well regions, wherein each of the first and second p-type well regions has a channel region adjacent the JFET region;

first and second n-type source regions on each of the first and second p-type well regions and adjacent the channel regions opposite the JFET region, wherein the first and second n-type source regions have a higher dopant concentration than the n-type drift layer;

source ohmic contacts on each of the first and second n-type source regions;

a gate dielectric layer on the JFET region and channel regions;

a gate layer on the gate dielectric layer;

an interlayer dielectric layer on the gate layer; and

first and second p-type body contact regions on the n-type drift layer and adjacent the first and second n-type source regions opposite the channel regions, wherein the first and second p-type body contact regions have a higher dopant concentration than the first and second p-type well regions;

one or more n-type Schottky regions on the n-type drift layer adjacent one or more of the MOSFET cells; and

a source metal layer on and in contact with the source ohmic contacts and on and in contact with the one or more n-type Schottky regions, the source metal layer forming a Schottky contact with the one or more n-type Schottky regions;

wherein each of the one or more n-type Schottky regions is adjacent and between the p-type body contact regions of adjacent cells; and

wherein the gate layer extends over the JFET region and the adjacent channel regions in the plane of the device.

2. The multi-cell MOSFET device of claim 1, wherein the one or more n-type Schottky regions have a different dopant concentration than the n-type drift layer.

3. The multi-cell MOSFET device of claim 1, wherein the n-type JFET region has a different dopant concentration than the n-type drift layer.

4. The multi-cell MOSFET device of claim 1, further comprising a dielectric material over the source ohmic contacts and the one or more n-type Schottky regions, the device further comprising:

one or more source vias formed through the dielectric material over the source ohmic contacts; and

one or more Schottky vias formed through the dielectric material over the one or more n-type Schottky regions;

wherein the source metal layer is on the dielectric material and in the source and Schottky vias and wherein the source metal layer contacts the Schottky regions at the bottom of the Schottky vias and the source ohmic contacts at the bottom of the source vias.

5. The multi-cell MOSFET device of claim 1, wherein:

the first and second p-type well regions are elongate regions spaced from one another in an x direction and extending in a y direction perpendicular to the x direction; and

the n-type JFET region is an elongate region extending in the x direction between the first and second p-type well regions.

6. The multi-cell MOSFET device of claim 5, wherein the Schottky region comprises a single continuous elongate region extending in the y direction between p-type body contact regions of adjacent MOSFET cells.

7. The multi-cell MOSFET device of claim 6, wherein the first and second p-type body contact regions are elongate regions extending in the y direction.

8. The multi-cell MOSFET device of claim 1, further comprising dielectric material in the first and second p-type body contact regions.

9. The multi-cell MOSFET device of claim 4, further comprising dielectric material in the first and second p-type body contact regions.

10. The multi-cell MOSFET device of claim 1, wherein the device comprises one n-type Schottky region for each of the MOSFET cells.

11. The multi-cell MOSFET device of claim 1, wherein the device comprises less than one n-type Schottky region for each MOSFET cell.

12. The multi-cell MOSFET device of claim 1, wherein the device comprises an even number of MOSFET cells and one n-type Schottky region for every two MOSFET cells.

13. The multi-cell MOSFET device of claim 1, wherein the device is a SiC device.

16. The multi-cell MOSFET device of claim 1, wherein the source ohmic contacts are on the first and second p-type body contact regions adjacent the first and second source regions, respectively.

14. A method of making a multi-cell MOSFET device, the method comprising:

forming first and second p-type well regions in an n-type drift layer, wherein the n-type drift layer is on an n-type substrate and wherein the first and second p-type well regions are spaced apart forming an n-type Schottky region therebetween and wherein an n-type region of the drift layer adjacent the first and second well regions and opposite the n-type Schottky region forms first and second JFET regions;

forming first and second n-type source regions in each of the first and second p-type well regions respectively, wherein the n-type source regions are spaced from the first and second JFET regions leaving a p-type channel region between the n-type source regions and the JFET regions;

forming first and second p-type body contact regions adjacent and between the Schottky region and the first and second n-type source regions, respectively;

depositing a gate oxide layer on the first and second JFET regions and on adjacent channel regions;

depositing a gate layer on the gate oxide layer;

depositing an interlayer dielectric material on the gate layer;

forming source ohmic contacts on the first and second n-type source regions and on the adjacent first and second p-type body contact regions;

depositing a source metal layer on the source ohmic contacts and on the n-type Schottky region, wherein the source metal layer forms a Schottky contact with the n-type Schottky region; and

depositing final metal on the source metal layer.

15. The method of claim 14, further comprising, before depositing the source metal layer:

forming dielectric material over the source contacts and Schottky region;

forming one or more source vias through the dielectric material over the source contacts; and

forming one or more Schottky vias through the dielectric material over the Schottky region;

wherein depositing the source metal layer comprises depositing source metal in the source and Schottky vias, wherein the source metal layer contacts the source metal and Schottky region at the bottom of the source and Schottky vias, respectively.