Thin film transistor, array substrate and display panel having the same, and fabricating method thereof

• US 10,290,741 B2
• Filed: 11/08/2016
• Issued: 05/14/2019
• Est. Priority Date: 05/31/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Ju, Changcheng, Meng, Hu, Li, Yanzhao
• Primary Examiner(s): Turner, Brian
• Application Number:
  US15/529,682
• Publication Number:
  US 20180219100A1
• Time in Patent Office: 917 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/36 Micro- or nanomaterials
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The present application discloses a thin film transistor including a base substrate and an active layer on the base substrate having a first portion corresponding to a channel region, a second portion corresponding to a source electrode contact region, and a third portion corresponding to a drain electrode contact region. The second portion and the third portion include a three-dimensional nanocomposite material having a semiconductor material matrix and a plurality of nanopillars in the semiconductor material matrix.

Claims

1. A thin film transistor comprising a base substrate and an active layer on the base substrate having a first portion corresponding to a channel region, a second portion corresponding to a source electrode contact region, and a third portion corresponding to a drain electrode contact region;

wherein the second portion and the third portion comprise a three-dimensional nanocomposite material comprising a semiconductor material matrix and a plurality of nanopillars in the semiconductor material matrix;

a respective one of the plurality of nanopillars has an elongated shape, a longitudinal direction of the elongated shape substantially perpendicular to the base substrates;

a respective one of the plurality of nanopillars in the second portion has a top end electrically connected to and in direct contact with a source electrode of the thin film transistor, and a bottom end electrically connected to and in direct contact with the base substrate; and

a respective one of the plurality of nanopillars in the third portion has a top end electrically connected to and in direct contact with a drain electrode of the thin film transistor, and a bottom end electrically connected to and in direct contact with the base substrate.

2. The thin film transistor of claim 1, wherein the plurality of nanopillars comprises an inorganic perovskite material.

3. The thin film transistor of claim 2, wherein the inorganic perovskite material comprises one of LaNiO₃, SrRuO₃, La_0.67Sr_0.33MnO₃, superconducting yttrium-barium-copper-oxygen (YBCO), and superconducting lanthanum strontium cobalt oxide (LSCO).

4. The thin film transistor of claim 1, wherein the semiconductor material matrix comprises a semiconductor material comprising M1O_aN_b, wherein M1 is a single metal or a combination of metals, a>

0, and b≥

0.

5. The thin film transistor of claim 4, wherein the semiconductor material matrix comprises one or more of indium tin zinc oxide, hafnium indium zinc oxide, zinc oxide, and indium gallium zinc oxide.

6. The thin film transistor of claim 1, wherein a volume ratio between the plurality of nanopillars and the semiconductor material matrix is in a range of approximately 3:

7 to approximately 1;

9.

7. The thin film transistor of claim 6, wherein the plurality of nanopillars comprises LaNiO₃, and the semiconductor material matrix comprises zinc oxide;

and

a volume ratio between LaNiO₃ and zinc oxide is in a range of approximately 3;

7 to approximately 1;

9.

8. The thin film transistor of claim 1, further comprising a source electrode in the source electrode contact region in direct contact with the second portion;

and a drain electrode in the drain electrode contact region in direct contact with the third portion;

wherein the source electrode and the drain electrode are made of a metal material.

9. The thin film transistor of claim 8, wherein the source electrode and the drain electrode comprises one or more of molybdenum, gold, and aluminum.

10. The thin film transistor of claim 1, wherein the first portion comprise a three-dimensional nanocomposite material comprising a semiconductor material matrix and a plurality of nanopillars in the semiconductor material matrix;

and

a volume ratio between the plurality of nanopillars and the semiconductor material matrix in the first portion is less than that in the second portion and the third portion.

11. The thin film transistor of claim 1, wherein the first portion comprise a three-dimensional nanocomposite material comprising a semiconductor material matrix and a plurality of nanopillars in the semiconductor material matrix;

and

a distribution density of nanopillars in the second portion and the third portion is greater than that in the first portion.

12. The thin film transistor of claim 1, wherein the base substrate is a single crystal perovskite base substrate or a base substrate comprising a perovskite buffer sub-layer.

13. The thin film transistor of claim 12, wherein the single crystal perovskite base substrate or the perovskite buffer sub-layer comprises SiTiO₃.

14. A display panel, comprising a thin film transistor of claim 1.

15. A method of fabricating a thin film transistor having an active layer including a first portion corresponding to a channel region, a second portion corresponding to a source electrode contact region, and a third portion corresponding to a drain electrode contact region;

the method comprising forming the active layer on a base substrate;

wherein forming the active layer comprises forming the second portion and the third portion using a three-dimensional nanocomposite material comprising a semiconductor material matrix and a plurality of nanopillars in the semiconductor material matrix;

a respective one of the plurality of nanopillars is formed to have an elongated shape, a longitudinal direction of the elongated shape substantially perpendicular to the base substrate;

a respective one of the plurality of nanopillars in the second portion is formed to have a top end electrically connected to and in direct contact with a source electrode of the thin film transistor, and a bottom end electrically connected to and in direct contact with the base substrate; and

a respective one of the plurality of nanopillars in the third portion is formed to have a top end electrically connected to and in direct contact with a drain electrode of the thin film transistor, and a bottom end electrically connected to and in direct contact with the base substrate.

16. A method of fabricating a thin film transistor having an active layer including a first portion corresponding to a channel region, a second portion corresponding to a source electrode contact region, and a third portion corresponding to a drain electrode contact region;

the method comprising forming the active layer on a base substrate;

wherein forming the active layer comprises forming the second portion and the third portion using a three-dimensional nanocomposite material comprising a semiconductor material matrix and a plurality of nanopillars in the semiconductor material matrix;

wherein the plurality of nanopillars are formed to extend substantially along a direction perpendicular to the base substrate; and

the plurality of nanopillars are formed using an inorganic perovskite material;

wherein forming the active layer comprises;

co-depositing a semiconductor material and the inorganic perovskite material on the base substrate to form a three-dimensional nanocomposite composite layer comprising the semiconductor material and the inorganic perovskite material; and

the base substrate is a single crystal perovskite base substrate or a base substrate comprising a perovskite buffer layer;

wherein the co-depositing is performed by pulsed laser deposition during which the inorganic perovskite material self-assembles into the plurality of nanopillars in the semiconductor material matrix.

17. The method of claim 16, wherein the pulsed laser deposition is performed at a laser pulse frequency and a deposition duration so that a volume ratio between the plurality of nanopillars and the semiconductor material matrix is in a range of approximately 3:

7 to approximately 1;

9.

18. The method of claim 16, wherein the pulsed laser deposition is performed at a deposition temperature in a range of approximately 600 degrees to approximately 700 degrees, and in an oxygen atmosphere under a pressure in a range of approximately 80 mTor to approximately 120 mTor.