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Reception interface circuits supporting multiple communication standards and memory systems including the same

  • US 10,291,275 B2
  • Filed: 01/03/2017
  • Issued: 05/14/2019
  • Est. Priority Date: 03/31/2016
  • Status: Active Grant
First Claim
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1. A reception interface circuit comprising:

  • a termination circuit configured to change a termination mode in response to a termination control signal;

    a buffer configured to change a reception characteristic in response to a buffer control signal;

    an interface controller configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode;

    wherein the termination circuit includesa first sub termination circuit configured to control an electrical connection between an input-output node and a first power supply voltage in response to a first switch control signal, anda second sub termination circuit configured to control an electrical connection between the input-output node and a second power supply voltage in response to a second switch control signal, the second power supply voltage lower than the first power supply voltage; and

    wherein the buffer includesa first reception buffer including a plurality of first differential input pairs of transistors, the plurality of first differential input pairs of transistors including both a first N-type differential input pair of NMOS transistors and a first P-type differential input pair of PMOS transistors,a second reception buffer including a single second differential input pair of transistors, the single second differential input pair of transistors being a P-type differential input pair of PMOS transistors, anda third reception buffer including a single third differential input pair of transistors, the single third differential input pair of transistors being an N-type differential input pair of NMOS transistors.

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