Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence

• US 10,291,386 B2
• Filed: 09/29/2017
• Issued: 05/14/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Meninger, Scott E.
• Primary Examiner(s): Wong, Linda
• Application Number:
  US15/721,334
• Publication Number:
  US 20190103956A1
• Time in Patent Office: 592 Days
• Field of Search: 375219, 375220, 375222, 37524026, 37524028, 375254, 375286, 375294, 375293, 375288, 375295, 375316, 375354, 375371, 375373-376
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

Claims

1. A circuit on a chip for serial data applications, the circuit comprising:

a common phase-locked loop (PLL) having a multiplying factor, the common PLL configured to receive an off-chip reference clock signal generated external to the chip and produce an on-chip reference clock signal, the on-chip reference clock signal higher in frequency relative to the off-chip reference clock signal; and

a plurality of serializer/deserializer (SerDes) lanes each including a respective transmitter, a respective receiver, and a respective fractional-N (frac-N) PLL including a respective divider with a respective divide value, the on-chip reference clock signal distributed to each respective frac-N PLL for use in generating a respective output clock signal with a respective frequency, the respective transmitter and receiver of each SerDes lane configured to operate at respective transmit and receive data rates that are based on the respective frequency and independent of data rates of other SerDes lanes of the plurality of SerDes lanes, the multiplying factor configured to suppress a portion of quantization noise, the portion introduced by modulating the respective divide value of the respective divider of each respective frac-N PLL of the plurality of SerDes lanes.

2. The circuit of claim 1, wherein the off-chip reference clock signal is configured to operate in a low frequency range of 100 MHz to 156 MHz and the on-chip reference clock signal is configured to operate in a higher frequency range of 400 MHz to 600 MHz.

3. The circuit of claim 1, wherein the circuit is configured to suppress a respective modulation noise, generated by each respective frac-N PLL of the plurality of SerDes lanes, by increasing frequency of the respective modulation noise to enable each respective frac-N PLL to filter the respective modulation noise.

4. The circuit of claim 1, wherein each respective frac-N PLL of the plurality of SerDes lanes further includes a respective sigma-delta modulator configured to modulate, randomly, the respective divide value of the respective divider.

5. The circuit of claim 1, wherein the common PLL is an integer PLL.

6. The circuit of claim 1, wherein the portion is an initial portion and wherein each respective frac-N PLL of the plurality of SerDes lanes further includes a respective out-of-band parasitic pole configured to suppress a remaining portion of the quantization noise, the remaining portion at higher offset frequencies relative to offset frequencies of the initial portion, the initial portion and the remaining portion suppressed below a noise level of noise generated from intrinsic phase detector and voltage controlled oscillator (VCO) noise sources on the chip.

7. The circuit of claim 1, wherein the common PLL is a first integer PLL, wherein each respective frac-N PLL of the plurality of SerDes lanes further includes a respective out-of-band parasitic pole configured high enough to not affect closed-loop behavior of the respective frac-N PLL, and wherein each respective out-of-band parasitic pole of each respective frac-N PLL of the plurality of SerDes lanes in combination with configuration of the multiplying factor enable jitter and phase noise performance of each respective frac-N PLL of the plurality of SerDes lanes to be comparable to that of a second integer PLL that employs a same integer divide value as the respective frac-N PLL.

8. The circuit of claim 1, wherein each respective frac-N PLL of the plurality of SerDes lanes further includes a respective sigma-delta modulator and wherein each respective frac-N PLL of the plurality of SerDes lanes has an order that is lower relative to that of the respective sigma-delta modulator.

9. The circuit of claim 8, wherein the order of each respective frac-N PLL of the plurality of SerDes lanes is two and that of the respective sigma-delta modulator is three.

10. The circuit of claim 1, wherein each respective frac-N PLL of the plurality of SerDes lanes further includes a respective spread spectrum clock (SSC) pattern generator configured to modulate the respective frac-N PLL, directly, according to a respective SSC profile.

11. The circuit of claim 1, wherein:

the chip is a physical layer device (PHY);

each SerDes lane is configured to employ the respective transmit and receive data rates to communicate with a respective media access controller (MAC); and

the respective transmit and receive data rates are configured independent of data rates employed by other SerDes lanes of the PHY for communicating with other MACs.

12. A method for achieving serializer/deserializer (SerDes) lane datarate independence, the method comprising:

producing an on-chip reference clock signal from a common phase-locked loop (PLL) having a multiplying factor, the common PLL on a chip, the on-chip reference clock signal produced based on an off-chip reference clock signal generated external to the chip, the on-chip reference clock signal higher in frequency relative to the off-chip reference clock signal; and

distributing the on-chip reference clock signal to each respective fractional-N (frac-N) PLL of a plurality of SerDes lanes each including a respective transmitter, a respective receiver, and a respective frac-N PLL including a respective divider with a respective divide value;

modulating the respective divide value of the respective divider of each respective frac-N PLL of the plurality of SerDes lane, the multiplying factor configured to suppress a portion of quantization noise introduced by the modulating;

generating a respective output clock signal with a respective frequency from each respective frac-N PLL based on the on-chip reference clock signal distributed; and

operating each respective transmitter and receiver of each SerDes lane at respective transmit and receive data rates that are based on the respective frequency and independent of data rates of other SerDes lanes of the plurality of SerDes lanes.

13. The method of claim 12, further comprising operating the off-chip reference clock signal in a low frequency range of 100 MHz to 156 MHz and operating the on-chip reference clock signal in a higher frequency range of 400 MHz to 600 MHz.

14. The method of claim 12, further comprising suppressing a respective modulation noise, generated by each respective frac-N PLL of the plurality of SerDes lanes, by increasing frequency of the respective modulation noise to enable each respective frac-N PLL to filter the respective modulation noise.

15. The method of claim 12, wherein each respective frac-N PLL of the plurality of SerDes lanes further includes a respective sigma-delta modulator and wherein the modulating includes employing each respective sigma-delta modulator to modulate, randomly, the respective divide value of the respective divider.

16. The method of claim 12, wherein the common PLL is an integer PLL.

17. The method of claim 12, wherein the portion is an initial portion, wherein each respective frac-N PLL of the plurality of SerDes lanes further includes a respective out-of-band parasitic pole, and wherein the method further comprises configuring each respective out-of-band parasitic pole to suppress a remaining portion of the quantization noise, the remaining portion at higher offset frequencies relative to offset frequencies of the initial portion, the initial portion and the remaining portion suppressed below a noise level of noise generated from intrinsic phase detector and voltage controlled oscillator (VCO) noise sources on the chip.

18. The method of claim 12, wherein the common PLL is a first integer PLL, wherein each respective frac-N PLL of the plurality of SerDes lanes further includes a respective out-of-band parasitic pole, and wherein the method further comprises configuring each respective out-of-band parasitic pole of each respective frac-N PLL of the plurality of SerDes to be high enough to not affect closed-loop behavior of the respective frac-N PLL and wherein each respective out-of-band parasitic pole of each respective frac-N PLL of the plurality of SerDes lanes in combination with configuration of the multiplying factor enable jitter and phase noise performance of each respective frac-N PLL of the plurality of SerDes lanes to be comparable to that of a second integer PLL that employs a same integer divide value as the respective frac-N PLL.

19. The method of claim 12, wherein each respective frac-N PLL of the plurality of SerDes lanes further includes a respective sigma-delta modulator and wherein the method further comprises configuring each respective frac-N PLL of the plurality of SerDes lanes to have an order that is lower relative to that of the respective sigma-delta modulator.

20. The method of claim 19, wherein the order of each respective frac-N PLL of the plurality of SerDes lanes is two and that of the respective sigma-delta modulator is three.

21. The method of claim 12, wherein each respective frac-N PLL of the plurality of SerDes lanes further includes a respective spread spectrum clock (SSC) pattern generator and the method further comprises configuring each respective SSC pattern generator to modulate the respective frac-N PLL, directly, according to a respective SSC profile.

22. The method of claim 12, wherein the chip is a physical layer device (PHY), and the method further comprises configuring each SerDes lane to employ respective transmit and receive data rates to communicate with a respective media access controller (MAC) and configuring the respective transmit and receive data rates independent of data rates employed by other SerDes lanes of the PHY for communicating with other MACs.

23. A circuit on a chip for serial data applications, the circuit comprising:

a common phase-locked loop (PLL), the common PLL configured to receive an off-chip reference clock signal generated external to the chip and produce an on-chip reference clock signal, the on-chip reference clock signal higher in frequency relative to the off-chip reference clock signal; and

a plurality of serializer/deserializer (SerDes) lanes each including a respective transmitter, a respective receiver, and a respective fractional-N (frac-N) PLL including a respective sigma-delta modulator, the on-chip reference clock signal distributed to each respective frac-N PLL for use in generating a respective output clock signal with a respective frequency, the respective transmitter and receiver of each SerDes lane configured to operate at respective transmit and receive data rates that are based on the respective frequency and independent of data rates of other SerDes lanes of the plurality of SerDes lanes, wherein each respective frac-N PLL of the plurality of SerDes lanes has an order that is lower relative to that of the respective sigma-delta modulator.

24. A method for achieving serial/deserializer (SerDes) lane datarate independence, the method comprising:

producing an on-chip reference clock signal from a common phase-locked loop (PLL) on a chip based on an off-chip reference clock signal generated external to the chip, the on-chip reference clock signal higher in frequency relative to the off-chip reference clock signal;

distributing the on-chip reference clock signal to each respective fractional-N (frac-N) PLL of a plurality of SerDes lanes each including a respective transmitter, a respective receiver, and a respective frac-N PLL including a respective sigma-delta modulator, each respective frac-N PLL of the plurality of SerDes lanes configured to have an order that is lower relative to that of the respective sigma-delta modulator;

generating a respective output clock signal with a respective frequency from each respective frac-N PLL based on the on-chip reference clock signal distributed; and

operating each respective transmitter and receiver of each SerDes lane at respective transmit and receive data rates that are based on the respective frequency and independent of data rates of other SerDes lanes of the plurality of SerDes lanes.

25. A circuit on a chip for serial data applications, the circuit comprising:

a common phase-locked loop (PLL) having a multiplying factor, the common PLL configured to receive an off-chip reference clock signal generated external to the chip and to produce an on-chip reference clock signal, the on-chip reference clock signal higher in frequency relative to the off-chip reference clock signal; and

a serializer/deserializer (SerDes) lane, the SerDes lane including a fractional-N (frac-N) PLL, the frac-N PLL including a divider with a divide value, the on-chip reference clock signal distributed to the frac-N PLL, the multiplying factor configured to suppress a portion of quantization noise, the portion introduced by modulating the divide value of the divider of the frac-N PLL.

26. A method comprising:

producing an on-chip reference clock signal from a common phase-locked loop (PLL) having a multiplying factor, the common PLL on a chip, the on-chip reference clock signal produced based on an off-chip reference clock signal generated external to the chip, the on-chip reference clock signal higher in frequency relative to the off-chip reference clock signal;

distributing the on-chip reference clock signal to a fractional-N (frac-N) PLL of a serializer/deserializer (SerDes) lane, the frac-N PLL including a respective divider with a respective divide value;

modulating the divide value of the divider of the frac-N PLL of the SerDes lane, the multiplying factor configured to suppress a portion of quantization noise introduced by the modulating.

27. A circuit on a chip for serial data applications, the circuit comprising:

a common phase-locked loop (PLL), the common PLL configured to receive an off-chip reference clock signal generated external to the chip and to produce an on-chip reference clock signal, the on-chip reference clock signal higher in frequency relative to the off-chip reference clock signal; and

a serializer/deserializer (SerDes) lane including a fractional-N (frac-N) PLL, the frac-N PLL including a sigma-delta modulator, the on-chip reference clock signal distributed to the frac-N PLL, the frac-N PLL configured to have an order that is lower relative to that of the sigma-delta modulator of the frac-N PLL of the SerDes lane.

28. A method comprising:

producing an on-chip reference clock signal from a common phase-locked loop (PLL) on a chip based on an off-chip reference clock signal generated external to the chip, the on-chip reference clock signal higher in frequency relative to the off-chip reference clock signal; and

distributing the on-chip reference clock signal to a fractional-N (frac-N) PLL of a serializer/deserializer (SerDes) lane, the frac-N PLL including a sigma-delta modulator, the frac-N PLL configured to have an order that is lower relative to that of the sigma-delta modulator of the frac-N PLL of the SerDes lane.