Generating, at least in part, and/or receiving, at least in part, at least one request

• US 10,291,542 B2
• Filed: 07/02/2012
• Issued: 05/14/2019
• Est. Priority Date: 09/12/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wang, Ren, Tai, Tsung-Yuan Charles, Tsai, Jr-Shian
• Primary Examiner(s): Rivas, Salvador E
• Application Number:
  US13/540,246
• Publication Number:
  US 20130170349A1
• Time in Patent Office: 2,507 Days
• CPC Class Codes: H04L 1/0018 based on latency requirement
• CPC Class Codes: H04L 1/1835 Buffer management
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 27/2666 Acquisition of further OFDM parameters, e.g. bandwidth, subcarrier spacing, or guard interval length
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 47/722 at the destination endpoint, e.g. reservation of terminal resources or buffer space
• CPC Class Codes: H04L 47/748 Negotiation of resources, e.g. modification of a request
• CPC Class Codes: H04L 67/125 involving control of end-device applications over a network
• CPC Class Codes: H04L 67/145 avoiding end of session, e.g. keep-alive, heartbeats, resumption message or wake-up for inactive or interrupted session
• CPC Class Codes: H04L 67/59 Providing operational support to end devices by off-loading in the network or by emulation, e.g. when they are unavailable
• CPC Class Codes: H04N 1/33376 according to characteristics or state of one of the communicating parties, e.g. available memory capacity
• CPC Class Codes: H04W 28/0236 radio quality, e.g. interference, losses or delay
• CPC Class Codes: H04W 28/0908 based on time, e.g. for a critical period only
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request that at least one network node generate, at least in part, information. The information may be to permit selection, at least in part, of (1) at least one power consumption state of the at least one network node, and (2) at least one time period. The at least one time period may be to elapse, after receipt by at least one other network node of at least one packet, prior to requesting at least one change in the at least one power consumption state. The at least one packet may be to be transmitted to the at least one network node. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

Claims

1. Computer-readable memory storing one or more instructions that when executed by a machine result in execution of operations to:

determine a time value, said operations to determine the time value comprising operations to;

determine a parameter of a first time duration based, at least in part, on a transmit buffer amount;

cause transmission of the parameter of the first time duration to a link partner;

receive a second time duration indicating a resume latency period from the link partner;

cause transmission of a wake signal to the link partner; and

based, at least in part, on the determined time value, (1) buffer packets destined for the link partner in the transmit buffer, and (2) delay transmission of the packets to the link partner until after the transmission of the wake signal to the link partner.

2. The computer-readable memory of claim 1, wherein the transmit buffer amount comprises an amount within a transmit buffer shared by multiple channels.

3. The computer-readable medium of claim 1, wherein the machine comprises a network interface controller (NIC).

4. A method, comprising:

at a first network device;

determining a time value, said determining the time value comprising;

determining a parameter of a first time duration based, at least in part, on a transmit buffer amount;

causing transmission of the parameter of the first time duration to a link partner;

receiving a second time duration indicating a resume latency period from the link partner;

causing transmission of a wake signal to the link partner; and

based, at least in part, on the time value, (1) buffering packets destined for the link partner in the transmit buffer, and (2) delaying transmission of the packets to the link partner until after causing transmission of the wake signal to the link partner.

5. The method of claim 4, further comprising determining the transmit buffer amount as a portion of a transmit buffer shared by multiple channels.

6. The method of claim 4, further comprising:

at the second network device;

determining the second time duration.

7. The method of claim 6, wherein the determining the second time duration comprises determining based, at least in part, on a receive buffer amount of the second network device.

8. The method of claim 6, wherein the determining the second time duration comprises determining based, at least in part, on a power consumption state available to the second network device.

9. An apparatus, comprising:

circuitry, when in operation, to;

determine a time value, said operations to determine the time value comprising operations to;

determine a parameter of a first time duration based, at least in part, on a transmit buffer amount;

cause transmission of the parameter of the first time duration to a link partner;

receive a second time duration indicating a resume latency period from the link partner;

cause transmission of a wake signal to the link partner; and

based, at least in part, on the determined time value, (1) buffer packets destined for the link partner in the transmit buffer, and (2) delay transmission of the packets to the link partner until after transmission of the wake signal to the link partner.

10. The apparatus of claim 9, wherein the apparatus comprises a network interface controller (NIC) having a Peripheral Component Interconnect (PCI) interface.

11. The apparatus of claim 9, wherein the apparatus comprises a motherboard having at least one processor and a chipset.