Clock management using full handshaking
First Claim
Patent Images
1. A system on chip (SoC) comprising:
- a plurality of intellectual property (IP) blocks; and
a clock management unit (CMU) performing clock gating on at least one of the IP blocks, one of the IP blocks providing a request signal to the CMU indicating the one of IP blocks desires to enter a selected one of a sleep mode and an active mode,wherein the IP blocks and the CMU interface with one another using a full handshake method,wherein the CMU outputs a clock signal and acknowledgement signal (ACK) to the one of the IP-blocks in response to the request signal indicating the one of the IP blocks desires to enter the active mode, and activates the Ack signal upon determining the output clock signal is stable.
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Abstract
A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.
68 Citations
25 Claims
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1. A system on chip (SoC) comprising:
- a plurality of intellectual property (IP) blocks; and
a clock management unit (CMU) performing clock gating on at least one of the IP blocks, one of the IP blocks providing a request signal to the CMU indicating the one of IP blocks desires to enter a selected one of a sleep mode and an active mode,wherein the IP blocks and the CMU interface with one another using a full handshake method, wherein the CMU outputs a clock signal and acknowledgement signal (ACK) to the one of the IP-blocks in response to the request signal indicating the one of the IP blocks desires to enter the active mode, and activates the Ack signal upon determining the output clock signal is stable. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
- a plurality of intellectual property (IP) blocks; and
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12. A clock gating component comprising:
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a clock control circuit generating an operating clock signal; and a channel management (CM) circuit receiving a request signal across a communication channel from an external device, and forwarding the request signal to the clock control circuit, wherein the clock control circuit transmits a clock request to a parent control circuit based on the request signal, receives a first acknowledgement (Ack) signal from the parent control circuit, selectively provides the operating clock signal to the external device according to the first Ack from the parent control circuit and provides a second acknowledgement (Ack) signal to the CM circuit indicating the clock control circuit has received the request signal, wherein the clock control circuit provides the operating clock signal to the external device when the first Ack indicates the operating clock signal is stable. - View Dependent Claims (13, 14, 15, 16)
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17. A clock multiplexer (MUX) component comprising:
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a clock control circuit selecting one of a first clock signal and a second clock signal based on a first selection signal, and generating an operating clock signal based on the selected clock signal; and a channel management (CM) circuit receiving a request signal across a communication channel from an external device, and forwarding the request signal to the clock control circuit, wherein the clock control circuit transmits a clock request to a parent control circuit based on the request signal, receives a first acknowledgement (Ack) signal from the parent control circuit, selectively outputs the operating clock signal in response to the first Ack signal, and outputs a second acknowledgement (Ack) signal to the CM circuit indicating the clock control circuit has received the request signal, and wherein the clock control circuit outputs the operating clock signal when the first Ack indicates the operating clock signal is stable. - View Dependent Claims (18, 19, 20, 21)
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22. A clock dividing component comprising:
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a clock control circuit performing a dividing operation on an input clock signal to generate a divided clock signal, and generating an operating clock signal based on the divided clock signal; and a channel management (CM) circuit receiving a request signal across a communication channel from an external device, and forwarding the request signal to the clock control circuit, wherein the clock control circuit transmits a clock request to a parent control circuit based on the request signal, receives a first acknowledgement (Ack) signal from the parent control circuit, selectively outputs the operating clock signal in response to the first Ack signal, and outputs a second acknowledgement (Ack) signal to the CM circuit indicating the clock control circuit has received the request signal, and wherein the clock control circuit outputs the operating clock signal when the first Ack indicates the operating clock signal is stable. - View Dependent Claims (23)
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24. A method of operating a clock management unit (CMU), the method comprising:
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the CMU determining whether a request signal received from an intellectual property (IP) block indicates the IP block desires to enter a selected one of an active mode and a sleep mode; the CMU outputting an acknowledgement (Ack) signal and a clock signal to the IP block when the request signal indicates the IP block desires to enter the active mode; the CM setting the Ack signal to an activated level upon determining the output clock signal is stable; and the CMU setting the Ack signal to a deactivated level when the clock request signal indicates the IP block desires to enter the sleep mode. - View Dependent Claims (25)
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Specification