Semiconductor device, semiconductor system, and method of operating the semiconductor device

• US 10,296,066 B2
• Filed: 01/25/2017
• Issued: 05/21/2019
• Est. Priority Date: 01/25/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ah Chan, Lee, Jae Gon, Lee, Min Joung
• Primary Examiner(s): Nguyen, Phuongchau Ba
• Application Number:
  US15/415,106
• Publication Number:
  US 20170214480A1
• Time in Patent Office: 846 Days
• Field of Search: 370519
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04J 3/14 Monitoring arrangements for SDH/SONET rings H04J3/085
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system on chip (SoC) includes a control circuit configured to determine whether a requested operating mode is one of a functional mode and a monitoring mode. The control circuit is configured to provide a request signal to at least one clock circuit to request at least one clock signal and selectively output one of the at least one clock signal in response to at least one acknowledgment signal received from the at least one clock circuit, when the requested operating mode is the functional mode. The control circuit is configured to selectively output one of the at least one clock signal without providing the request signal, when the requested operating mode is the monitoring mode.

Claims

1. A system on chip (SoC) comprising:

a clock management unit (CMU) comprising a plurality of clock circuits, a control circuit and an output pin, the CMU configured to receive a request signal from a first external device or the control circuit, and generate a clock signal using the plurality of clock circuits in response to the request signal,

wherein the control circuit is configured to determine whether the CMU is to operate in one of a functional mode and a monitoring mode,

wherein the control circuit is configured to provide the request signal to at least one of the clock circuits and selectively provide one of a plurality of outputs of the clock circuits to the output pin in response to at least one acknowledgment signal received from at least one of the clock circuits, when the CMU is determined to operate in the functional mode, and

wherein the control circuit is configured to selectively provide one of the plurality of outputs to the output pin without providing the request signal to any of the clock circuits, when the CMU is determined to operate in the monitoring mode.

2. The SoC of claim 1, wherein the control circuit comprises a finite state machine configured to determine whether the CMU is to operate in the functional mode or the monitoring mode in response to a received mode control signal.

3. The SoC of claim 1, wherein the outputs provide at least one internal clock signal and the control circuit is driven by a reference clock signal of a different clock domain than the at least one internal clock signal.

4. The SoC of claim 1, wherein the control circuit comprises a clock gating circuit that is configured to selectively provide the one output to the output pin in response to an enable signal.

5. The SoC of claim 1, wherein the control circuit comprises:

a first clock control circuit configured to receive the at least one acknowledgement signal, provide the request signal, and output a select signal; and

a multiplexer configured to receive the outputs and provide one of the received outputs based on receipt of the select signal.

6. The SoC of claim 5, wherein the first clock control circuit changes the select signal to a new value only after receiving an acknowledgement signal from a first one of the clock circuits generating a clock signal currently being output by the multiplexer and an acknowledgement signal from a second other one of the clock circuits generating a clock signal to next be output by the multiplexer.

7. The SoC of claim 5, wherein control circuit further comprises:

a second clock control circuit configured to receive the at least one acknowledgement signal from the first clock control circuit, provide the request signal to the first clock control circuit, and output a division ratio; and

a clock dividing circuit configured to perform a dividing operation on the clock signal output by the multiplexer using the dividing ratio to generate a divided clock signal, and output the divided clock signal as the one output.

8. The SoC of claim 7, wherein the second clock control circuit changes the division ratio to a new value only after receiving acknowledgement signal from the first clock control circuit.

9. The SoC of claim 1, wherein the output pin is configured to provide the one output to a second external device.

10. The SoC of claim 1, wherein the clock circuits communicate with one another using synchronous handshaking to provide the clock signal to the first external device, wherein the first external device is an intellectual property (IP) block.

11. A semiconductor system comprising the SoC of claim 10.

12. The semiconductor system of claim 11, further comprising a memory, wherein the IP block is a memory controller configured to control the memory.

13. The semiconductor system of claim 11, further comprising a display, wherein the IP block is a display controller configured to control the display.

14. The semiconductor system of claim 11, further comprising a network device, wherein the IP block is a network controller configured to control the network device.

15. The semiconductor system of claim 11, further comprising a bus enabling the SoC to communicate with the IP block.

16. A clock signal output circuit configured to communicate with a clock management unit (CMU) comprising a plurality of clock circuits, the CMU configured to generate a clock signal using the clock circuits in response to a request signal, the clock signal output circuit comprising:

a clock multiplexing circuit configured to receive a plurality of clock signals from a outputs of the plurality of clock circuits,

a logic circuit; and

an output pin,

wherein the logic circuit outputs a control signal to the clock multiplexing circuit when a current mode is set to a functional mode,

wherein the clock multiplexing circuit outputs the request signal to the clock circuits in response to the control signal, and outputs one of the outputs to the output pin after receiving at least one acknowledgement signal from at least one of the clock circuits, and

wherein the clock multiplexing circuit outputs one of the outputs to the output pin without providing the request signal to any of the clock circuits when the current mode is set to a monitoring mode.

17. The clock signal output circuit of claim 16, further comprising a clock gate circuit configured to selectively output the one output in response to an enable signal.

18. A system on chip comprising the clock signal output circuit of claim 16.

19. A clock signal output circuit configured to communicate with a clock management unit (CMU) comprising a clock circuit, the CMU configured to generate a clock signal using the clock circuit in response to a request signal, the clock signal output circuit comprising:

a clock dividing circuit configured to perform a dividing operation on the clock signal output by the clock circuit to generate a divided clock signal;

a logic circuit; and

an output pin,

wherein the logic circuit outputs a signal to the clock dividing circuit when a current mode is set to a functional mode,

wherein the clock dividing circuit outputs the request signal to the clock circuit in response to the control signal, and outputs the divided clock signal to the output pin after receiving an acknowledgement signal from the clock circuit, and

wherein the clock dividing circuit outputs the divided clock signal to the output pin without providing the request signal to the clock circuit when the current mode is set to a monitoring mode.

20. The clock signal output circuit of claim 19, further comprising a clock gate circuit configured to selectively output the divided clock signal in response to an enable signal.

21. A system on chip comprising the clock signal output circuit of claim 19.

22. A method of operating a system on chip (SoC) comprising a clock management unit (CMU) comprising a plurality of clock circuits, a control circuit and an output pin, the CMU configured to receive a request signal from a first external device or the control circuit, and generate a clock signal using the plurality of clock circuits in response to the request signal, the method comprising:

determining, by the control circuit of the SoC, whether to operate in one of a functional mode and a monitoring mode;

when the control circuit determines to operate in the functional mode,

providing, by the control circuit, the request signal to at least one of the clock circuits of the SoC; and

providing, by the control circuit, one of a plurality of outputs of the clock circuits to the output pin after receiving at least one acknowledgement signal from at least one of the clock circuits,

when the control circuit determines to operate in the monitoring mode,

providing, by the control circuit, one of the outputs to the output pin without providing the request signal to any of the clock circuits.

23. The method of claim 22, further comprises applying a selection signal to a multiplexer of the control circuit to switch from a previous clock signal to a new clock signal only after receiving acknowledgement signals from the clock circuit providing the previous clock signal and the clock circuit providing the new clock signal.

24. The method of claim 23, further comprises applying a division ratio to a clock dividing circuit of the control circuit to perform a dividing operation on an output of the multiplexer using the division ratio only after receiving an acknowledgement signal from the multiplexer.