Source coordination of audio playback

• US 10,296,285 B2
• Filed: 08/15/2017
• Issued: 05/21/2019
• Est. Priority Date: 12/13/2016
• Status: Active Grant

• Current Assignee: B & W Group Ltd (Masimo Corporation)
• Original Assignee: EVA Automation, Inc.
• Inventors: Lay, Leo, Chadd, Adrian Harold, Wang, Haisong, Zhao, Shiwei, Li, Li, Yu, Gaylord
• Primary Examiner(s): Saunders, Jr., Joseph
• Application Number:
  US15/678,072
• Publication Number:
  US 20180165057A1
• Time in Patent Office: 644 Days
• CPC Class Codes: G06F 3/165 Management of the audio stream, e.g. setting of volume, audio stream path
• CPC Class Codes: H04H 60/80 characterised by transmission among terminal devices
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04J 3/0661 using timestamps
• CPC Class Codes: H04L 65/60 Network streaming of media packets
• CPC Class Codes: H04L 65/61 for supporting one-way streaming services, e.g. Internet radio
• CPC Class Codes: H04L 65/65 Network streaming protocols, e.g. real-time transport protocol [RTP] or real-time control protocol [RTCP]
• CPC Class Codes: H04L 65/80 Responding to QoS
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0016 correction of synchronization errors
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04M 1/72442 for playing music files
• CPC Class Codes: H04N 21/233 Processing of audio elementary streams monitoring, identification or recognition of audio in broadcast systems H04H60/58
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/8113 comprising music, e.g. song in MP3 format
• CPC Class Codes: H04R 2227/005 Audio distribution systems for home, i.e. multi-room use
• CPC Class Codes: H04R 2420/07 Applications of wireless loudspeakers or wireless microphones
• CPC Class Codes: H04R 27/00 Public address systems circuits for preventing acoustic reaction H04R3/02; circuits for distributing signals to loudspeakers H04R3/12; monitoring or testing arrangements for public address systems H04R29/007; amplifiers H03F
• CPC Class Codes: H04R 3/12 for distributing signals to two or more loudspeakers specially adapted for hearing aids H04R25/407
• CPC Class Codes: H04W 56/0015 : one node acting as a reference for the others
• CPC Class Codes: H04W 56/005 : compensating for timing error by adjustment in the receiver

Abstract

An electronic device that coordinates a playback operation is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may determine a remaining time offset between the clock and the second clock. Next, the interface circuit may modify a future time when the second electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and may transmit information to the second electronic device specifying the corrected future time.

Claims

1. An electronic device, comprising:

one or more antennas;

a clock circuit that is configured to provide a clock; and

an interface circuit communicatively coupled to the one or more antennas and the clock circuit, wherein the interface circuit is configured to;

receive, from the one or more antennas, packets associated with a second electronic device, wherein a given packet comprises a transmit time, based on a second clock in the second electronic device, when the second electronic device transmitted the given packet;

store receive times when the packets were received, wherein the receive times are based on the clock;

calculate, based on differences between the transmit times and the receive times, relative drift as a function of time between the clock and the second clock, wherein a given difference is between a given transmit time and a given receive time for a given packet, and wherein the calculation is based on unilateral communication of timing information between the second electronic device and the electronic device;

adjust, based on the relative drift, the clock circuit that provides the clock to eliminate the relative drift;

determine a remaining time offset between the clock and the second clock;

modify, based on the remaining time offset, a future time, when the second electronic device is to perform a playback operation, to determine a corrected future time; and

transmit, via the one or more antennas, information intended for the second electronic device specifying the corrected future time.

2. The electronic device of claim 1, wherein the transmit time is included in the given packet in one of:

a payload; and

a media access control (MAC) header.

3. The electronic device of claim 1, wherein the clock circuit further comprises:

an oscillator configured to provide a reference clock; and

a frequency-locked-loop (FLL) circuit, coupled to the oscillator, configured to generate the clock based on the reference clock; and

wherein the interface circuit is configured to eliminate the relative drift by modifying the FLL to adjust the clock.

4. The electronic device of claim 3, wherein modifying the FLL comprises changing a seed of a synthesizer in the FLL.

5. The electronic device of claim 1, wherein the transmit time and the receive time are stored on opposite ends of a payload of the given packet;

and

wherein the electronic device is configured to determine a duration of the payload and the interface circuit is configured to add the duration to the remaining offset time.

6. The electronic device of claim 1, wherein the transmit times comprise second counter values corresponding to the second clock and the receive times comprise counter values corresponding to the clock.

7. The electronic device of claim 1, wherein, prior to transmitting the information, the interface circuit is configured to transmit, via the one or more antennas, additional packets intended for the second electronic device that comprise audio data in payloads;

and

wherein the playback operation comprises outputting the audio data as sound.

8. The electronic device of claim 1, wherein the adjusting the clock and the modifying the future time coordinate the playback operation in a clock domain of the clock to within a predefined value of a clock domain of the second clock.

9. The electronic device of claim 1, wherein the packets comprise control packets.

10. The electronic device of claim 1, wherein the electronic device is a master and the second electronic device is a slave.

11. The electronic device of claim 1, wherein the receive times are associated with a wireless ranging capability of the interface circuit.

12. A non-transitory computer-readable storage medium for use with an electronic device, the computer-readable storage medium storing a program module that, when executed by an interface circuit in the electronic device, coordinates a playback operation by causing the electronic device to perform one or more operations comprising:

receiving, from one or more antennas in the electronic device, packets associated with a second electronic device, wherein a given packet comprises a transmit time, based on a second clock in the second electronic device, when the second electronic device transmitted the given packet;

storing receive times when the packets were received, wherein the receive times are based on a clock in the electronic device;

calculating, based on differences between the transmit times and the receive times, relative drift as a function of time between the clock and the second clock, wherein a given difference is between a given transmit time and a given receive time for a given packet, and wherein the calculation is based on unilateral communication of timing information between the second electronic device and the electronic device;

adjusting, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift;

determining a remaining time offset between the clock and the second clock;

modifying, based on the remaining time offset, a future time, when the second electronic device is to perform the playback operation, to determine a corrected future time; and

transmitting, via the one or more antennas, information intended for the second electronic device specifying the corrected future time.

13. The non-transitory computer-readable storage medium of claim 12, wherein the transmit time is included in the given packet in one of:

a payload; and

a media access control (MAC) header.

14. The non-transitory computer-readable storage medium of claim 12, wherein the transmit time and the receive time are stored in a payload of the given packet;

and

wherein the one or more operations comprise adding a duration of the packet to the remaining offset time.

15. The non-transitory computer-readable storage medium of claim 12, wherein, prior to the transmitting of the information, the one or more operations comprise transmitting, via the one or more antennas, additional packets intended for the second electronic device that comprise audio data in payloads;

and

wherein the playback operation comprises outputting the audio data as sound.

16. A method for coordinating a playback operation, comprising:

by an interface circuit of an electronic device;

receiving, from one or more antennas in the electronic device, packets associated with a second electronic device, wherein a given packet comprises a transmit time, based on a second clock in the second electronic device, when the second electronic device transmitted the given packet;

storing receive times when the packets were received, wherein the receive times are based on a clock in the electronic device;

calculating, based on differences between the transmit times and the receive times, relative drift as a function of time between the clock and the second clock, wherein a given difference is between a given transmit time and a given receive time for a given packet, and wherein the calculation is based on unilateral communication of timing information between the second electronic device and the electronic device;

adjusting, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift;

determining a remaining time offset between the clock and the second clock;

receiving, from the one or more antennas, information associated with the second electronic device specifying a future time, when the second electronic device is to perform the playback operation;

modifying, based on the remaining time offset, the future time to determine a corrected future time; and

transmitting, via the one or more antennas, information intended for the second electronic device specifying the corrected future time.

17. The method of claim 16, wherein the transmit time is included in the given packet in one of:

a payload; and

a media access control (MAC) header.

18. The method of claim 16, wherein the adjusting comprises modifying a seed of a synthesizer in a frequency-locked loop (FLL) in the clock circuit.

19. The method of claim 16, wherein the transmit time and the receive time are stored in a payload of the given packet;

and

wherein the method further comprises adding a duration of the packet to the remaining offset time.

20. The method of claim 16, wherein, prior to transmitting the information, the method further comprises transmitting, via the one or more antennas, additional packets intended for the second electronic device that comprise audio data in payloads;

and

wherein the playback operation comprises outputting the audio data as sound.