Maintaining coordination following a wireless reset

• US 10,296,286 B2
• Filed: 08/15/2017
• Issued: 05/21/2019
• Est. Priority Date: 12/13/2016
• Status: Active Grant

• Current Assignee: B & W Group Ltd (Masimo Corporation)
• Original Assignee: EVA Automation, Inc.
• Inventors: Lay, Leo, Chadd, Adrian Harold, Wang, Haisong, Zhao, Shiwei, Li, Li, Yu, Gaylord
• Primary Examiner(s): Han, Clemence S
• Application Number:
  US15/678,078
• Publication Number:
  US 20180167192A1
• Time in Patent Office: 644 Days
• CPC Class Codes: G06F 3/165 Management of the audio stream, e.g. setting of volume, audio stream path
• CPC Class Codes: H04H 60/80 characterised by transmission among terminal devices
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04J 3/0661 using timestamps
• CPC Class Codes: H04L 65/60 Network streaming of media packets
• CPC Class Codes: H04L 65/61 for supporting one-way streaming services, e.g. Internet radio
• CPC Class Codes: H04L 65/65 Network streaming protocols, e.g. real-time transport protocol [RTP] or real-time control protocol [RTCP]
• CPC Class Codes: H04L 65/80 Responding to QoS
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0016 correction of synchronization errors
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04M 1/72442 for playing music files
• CPC Class Codes: H04N 21/233 Processing of audio elementary streams monitoring, identification or recognition of audio in broadcast systems H04H60/58
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/8113 comprising music, e.g. song in MP3 format
• CPC Class Codes: H04R 2227/005 Audio distribution systems for home, i.e. multi-room use
• CPC Class Codes: H04R 2420/07 Applications of wireless loudspeakers or wireless microphones
• CPC Class Codes: H04R 27/00 Public address systems circuits for preventing acoustic reaction H04R3/02; circuits for distributing signals to loudspeakers H04R3/12; monitoring or testing arrangements for public address systems H04R29/007; amplifiers H03F
• CPC Class Codes: H04R 3/12 for distributing signals to two or more loudspeakers specially adapted for hearing aids H04R25/407
• CPC Class Codes: H04W 56/0015 : one node acting as a reference for the others
• CPC Class Codes: H04W 56/005 : compensating for timing error by adjustment in the receiver

Abstract

An electronic device that reduces relative drift is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may store the adjustments to the clock circuit. Furthermore, when a wireless reset occurs, the interface circuit may adapt the clock circuit based on the stored adjustments to reduce the relative drift while the interface circuit restores frequency lock with the second clock based on additional packets with additional transmit times that are received from the second electronic device.

Claims

1. An electronic device, comprising:

one or more antennas;

a clock circuit that is configured to provide a clock; and

an interface circuit communicatively coupled to the one or more antennas and the clock circuit, wherein the interface circuit is configured to;

receive, from the one or more antennas, packets associated with a second electronic device, wherein a given packet comprises a transmit time, based on a second clock in the second electronic device, when the second electronic device transmitted the given packet;

store receive times when the packets were received, wherein the receive times are based on the clock;

calculate, based on differences between the transmit times and the receive times, relative drift as a function of time between the clock and the second clock;

adjust, based on the relative drift, the clock circuit to eliminate the relative drift;

store adjustments to the clock circuit from the adjust operation; and

when the interface circuit or a second interface circuit in the second electronic device is reset, adapt the clock circuit based on the stored adjustments to reduce the relative drift while the interface circuit restores frequency lock with the second clock based on additional packets with additional transmit times that are received from the one or more antennas.

2. The electronic device of claim 1, wherein the clock circuit further comprises:

an oscillator configured to provide a reference clock; and

a frequency-locked-loop (FLL) circuit, coupled to the oscillator, configured to generate the clock based on the reference clock; and

wherein the adjustments are applied to a seed of a first synthesizer in the FLL.

3. The electronic device of claim 2, wherein the FLL comprises a second synthesizer that is configured to track the adjustments to the first synthesizer.

4. The electronic device of claim 1, wherein restoring the frequency lock occurs over a time interval;

and

wherein, prior to storing the adjustments, the interface circuit is configured to average the adjustments over a time scale corresponding to the time interval.

5. The electronic device of claim 1, wherein the transmit time is included in the given packet in one of;

a payload; and

a media access control (MAC) header.

6. The electronic device of claim 1, wherein the transmit times comprise second counter values corresponding to the second clock and the receive times comprise counter values corresponding to the clock;

wherein, when the interface circuit or the second interface circuit is reset, a counter in the electronic device that provided the counter values in the receive times is reset; and

wherein the interface circuit comprises a sample-and-hold circuit that is configured to mirror a current counter value of the counter when the interface circuit or the second interface circuit is reset.

7. The electronic device of claim 1, wherein the packets comprise control packets.

8. The electronic device of claim 1, wherein the receive times are associated with a wireless ranging capability of the interface circuit.

9. A method for reducing relative drift, comprising:

by an interface circuit of an electronic device;

receiving, from one or more antennas in the electronic device, packets associated with a second electronic device, wherein a given packet comprises a transmit time, based on a second clock in the second electronic device, when the second electronic device transmitted the given packet;

storing receive times when the packets were received, wherein the receive times are based on a clock in the electronic device;

calculating, based on differences between the transmit times and the receive times, the relative drift as a function of time between the clock and the second clock;

adjusting, based on the relative drift, a clock circuit in the electronic device that provides the clock to eliminate the relative drift;

storing adjustments to the clock circuit from the adjusting operation; and

when the interface circuit or a second interface circuit in the second electronic device is reset, adapting the clock circuit based on the stored adjustments to reduce the relative drift while the interface circuit restores frequency lock with the second clock based on additional packets with additional transmit times that are received from the one or more antennas.

10. An electronic device, comprising:

one or more antennas;

a clock circuit that is configured to provide a clock; and

an interface circuit communicatively coupled to the one or more antennas, wherein the interface circuit is configured to;

receive, from the one or more antennas, packets associated with a second electronic device, wherein a given packet comprises a transmit time, based on a second clock in the second electronic device, when the second electronic device transmitted the given packet;

store receive times when the packets were received, wherein the receive times are based on the clock;

calculate, based on differences between the transmit times and the receive times, relative drift as a function of time between the clock and the second clock;

adjust, based on the relative drift, the clock circuit to eliminate the relative drift;

store adjustments to the clock circuit from the adjust operation; and

adapt the clock circuit based on the stored adjustments to reduce the relative drift during a reset, the adapting being performed on a longer time scale than the adjusting.

11. The electronic device of claim 10, wherein the adapting is performed periodically.

12. The electronic device of claim 10, wherein the adapting reduces the relative drift when the interface circuit or a second interface circuit in the second electronic device is reset and while the interface circuit restores frequency lock with the second clock based on additional packets with the additional transmit times that are received from the one or more antennas.

13. The electronic device of claim 12, wherein restoring the frequency lock occurs over a time interval;

and

wherein, prior to storing the adjustments, the interface circuit is configured to average the adjustments over a time scale corresponding to the time interval.

14. The electronic device of claim 12, wherein the transmit times comprise second counter values corresponding to the second clock and the receive times comprise counter values corresponding to the clock;

wherein, when the interface circuit or the second interface circuit is reset, a counter in the electronic device that provided the counter values in the receive times is reset; and

wherein the interface circuit comprises a sample-and-hold circuit that is configured to mirror a current counter value of the counter when the interface circuit or the second interface circuit is reset.

15. The electronic device of claim 10, wherein the clock circuit further comprises:

an oscillator configured to provide a reference clock; and

a frequency-locked-loop (FLL) circuit, coupled to the oscillator, configured to generate the clock based on the reference clock; and

wherein the adjustments are applied to a seed of a first synthesizer in the FLL.

16. The electronic device of claim 15 wherein the FLL comprises a second synthesizer that is configured to track the adjustments to the first synthesizer.

17. The electronic device of claim 10, wherein the transmit time is included in the given packet in one of:

a payload; and

a media access control (MAC) header.

18. The electronic device of claim 10, wherein the packets comprise control packets.

19. The electronic device of claim 10, wherein the receive times are associated with a wireless ranging capability of the interface circuit.

20. A method for reducing relative drift, comprising:

by an interface circuit of an electronic device;

receiving, from one or more antennas in the electronic device, packets associated with a second electronic device, wherein a given packet comprises a transmit time, based on a second clock in the second electronic device, when the second electronic device transmitted the given packet;

storing receive times when the packets were received, wherein the receive times are based on a clock in the electronic device;

calculating, based on differences between the transmit times and the receive times, the relative drift as a function of time between the clock and the second clock;

adjusting, based on the relative drift, a clock circuit in the electronic device that provides the clock to eliminate the relative drift;

storing adjustments to the clock circuit from the adjusting operation; and

adapting the clock circuit based on the stored adjustments to reduce the relative drift during a reset, the adapting being performed on a longer time scale than the adjusting.