Thread transition management

• US 10,296,339 B2
• Filed: 08/11/2018
• Issued: 05/21/2019
• Est. Priority Date: 02/23/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Abernathy, Christopher M., Brown, Mary D., Eisen, Susan E., Kahle, James A., Le, Hung Q., Nguyen, Dung Q.
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US16/101,431
• Publication Number:
  US 20180349141A1
• Time in Patent Office: 283 Days
• Field of Search: None
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context

Abstract

A system and process for managing thread transitions includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A determination is made whether a quantity of the first-level registers needed to execute one or more threads exceeds a quantity of the first-level registers of the two data register sets. Responsive to determining that the quantity of the first-level registers needed to execute the one or more threads exceeds the quantity of the first-level registers of the two data register sets, a portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the one or more threads.

Claims

1. A computer program product for thread transition management, the computer program product comprising:

a non-transitory computer readable medium having computer readable program code embodied therewith, the computer readable program code comprising computer readable program code configured to;

cause a processor to access two data register sets coupled to a computer memory, the two data register sets usable by the processor as first-level registers for thread execution;

determine whether a quantity of the first-level registers needed to execute one or more threads exceeds a quantity of the first-level registers of the two data register sets; and

responsive to determining that the quantity of the first-level registers needed to execute the one or more threads exceeds the quantity of the first-level registers of the two data register sets, assign a portion of main memory or cache memory as second-level registers, the second-level registers serving as registers of at least one of the two data register sets for executing the one or more threads.

2. The computer program product of claim 1, wherein the computer readable program code is configured to cause the processor to use the second-level registers in a mirrored data processing mode and a split data processing mode.

3. The computer program product of claim 1, wherein the computer readable program code is configured to cause the processor to move thread data in at least one of the first-level registers to the second-level registers.

4. The computer program product of claim 1, wherein the computer readable program code is configured to cause the processor to move thread data in at least one of the second-level registers to the first-level registers.

5. The computer program product of claim 1, wherein the computer readable program code is configured to cause the processor to move thread data between the first-level registers and the second-level registers to address an imbalance of thread execution between the two data register sets.

6. A system comprising:

a computer memory;

two data register sets coupled to the computer memory; and

a processor coupled to the two data register sets, the two data register sets usable by the processor as first-level registers for thread execution, the processor configured to;

determine whether a quantity of the first-level registers needed to execute one or more threads exceeds a quantity of the first-level registers of the two data register sets; and

responsive to determining that the quantity of the first-level registers needed to execute the one or more threads exceeds the quantity of the first-level registers of the two data register sets, assign a portion of main memory or cache memory as second-level registers, the second-level registers serving as registers of at least one of the two data register sets for executing the one or more threads.

7. The system of claim 6, wherein the processor is configured to use the second-level registers in a mirrored data processing mode and a split data processing mode.

8. The system of claim 6, wherein the processor is further configured to move thread data in at least one of the first-level registers to the second-level registers.

9. The system of claim 6, wherein the processor is further configured to move thread data in at least one of the second-level registers to the first-level registers.

10. The system of claim 6, wherein the processor is further configured to move thread data between the first-level registers and the second-level registers to address an imbalance of thread execution between the two data register sets.

11. A method comprising:

providing two data register sets coupled to a processor;

using, by the processor, the two register sets as first-level registers for thread execution;

determining whether a quantity of the first-level registers needed to execute one or more threads exceeds a quantity of the first-level registers of the two data register sets; and

responsive to determining that the quantity of the first-level registers needed to execute the one or more threads exceeds the quantity of the first-level registers of the two data register sets, assigning a portion of main memory or cache memory as second-level registers, the second-level registers serving as registers of at least one of the two data register sets for executing the one or more threads.

12. The method of claim 11, further comprising using the second-level registers in a mirrored data processing mode and a split data processing mode.

13. The method of claim 11, further comprising moving thread data in at least one of the first-level registers to the second-level registers.

14. The method of claim 11, further comprising moving thread data in at least one of the second-level registers to the first-level registers.

15. The method of claim 11, further comprising moving thread data between the first-level registers and the second-level registers to address an imbalance of thread execution between the two data register sets.