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Data coherency model and protocol at cluster level

  • US 10,296,399 B2
  • Filed: 06/09/2016
  • Issued: 05/21/2019
  • Est. Priority Date: 12/27/2013
  • Status: Active Grant
First Claim
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1. A node for providing data coherency, the node comprising:

  • a central processing unit (CPU);

    a node memory comprising a node address map, wherein the node address map includes (i) a shared memory region that is mapped to a global memory shared between the node and other nodes, (ii) a reflected memory region that forms a portion of the global memory and is mapped to a space of the node memory that is not cacheable, and (iii) a semaphore region to provide a hardware assist for enforced data coherency of the global memory; and

    a fabric memory controller to manage access to the node memory by the other nodes.

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