Data coherency model and protocol at cluster level

• US 10,296,399 B2
• Filed: 06/09/2016
• Issued: 05/21/2019
• Est. Priority Date: 12/27/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Das Sharma, Debendra, Kumar, Mohan J., Fleischer, Balint
• Primary Examiner(s): Butler, Sarai E
• Application Number:
  US15/178,159
• Publication Number:
  US 20170046208A1
• Time in Patent Office: 1,076 Days
• Field of Search: 714 61
• CPC Class Codes: G06F 11/2017 where memory access, memory control or I/O control functionality is redundant redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material

Abstract

An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.

Claims

1. A node for providing data coherency, the node comprising:

a central processing unit (CPU);

a node memory comprising a node address map, wherein the node address map includes (i) a shared memory region that is mapped to a global memory shared between the node and other nodes, (ii) a reflected memory region that forms a portion of the global memory and is mapped to a space of the node memory that is not cacheable, and (iii) a semaphore region to provide a hardware assist for enforced data coherency of the global memory; and

a fabric memory controller to manage access to the node memory by the other nodes.

2. The node of claim 1, wherein the semaphore region comprises a directory for each shared block of memory of the global memory.

3. The node of claim 1, wherein the fabric memory controller is further to:

receive, from another node of the other nodes, a request for a lock associated with requested data stored in the share memory region;

grant, to the another node, the lock associated with the requested data based on the data contained in the directory; and

update the directory in response to the grant of the lock.

4. The node of claim 3, wherein to receive the request for the lock comprises to receive a read request from the another node to an address in the directory.

5. The node of claim 4, wherein the read request includes an address offset and a type of the lock is defined by a value of the offset.

6. The node of claim 4, wherein to grant the lock comprises to transmit an identifier of a destination node at which the requested data is stored.

7. The node of claim 1, wherein the fabric memory controller is further to facilitate access to the node memory by the other nodes while the CPU is in a failed state.

8. One or more machine-readable storage media comprising a plurality of instructions stored thereon that, when executed, cause a node to:

establish, in a node memory of the node, and address map, wherein the node address map includes (i) a shared memory region that is mapped to a global memory shared between the node and other nodes, (ii) a reflected memory region that forms a portion of the global memory and is mapped to a space of the node memory that is not cacheable, and (iii) a semaphore region to provide a hardware assist for enforced data coherency of the global memory; and

manage, by a fabric memory controller of the node, access to the node memory by the other nodes.

9. The one or more machine-readable storage media of claim 8, wherein the semaphore region comprises a directory for each shared block of memory of the global memory.

10. The one or more machine-readable storage media of claim 9, wherein the plurality of instructions, when executed, further cause node to:

receive, from another node of the other nodes, a request for a lock associated with requested data stored in the share memory region;

grant, to the another node, the lock associated with the requested data based on the data contained in the directory; and

update the directory in response to the grant of the lock.

11. The one or more machine-readable storage media of claim 10, wherein to receive the request for the lock comprises to receive a read request from the another node to an address in the directory.

12. The one or more machine-readable storage media of claim 11, wherein the read request includes an address offset and a type of the lock is defined by a value of the offset.

13. The one or more machine-readable storage media or more machine-readable storage media of claim 11, wherein to grant the lock comprises to transmit an identifier of a destination node at which the requested data is stored.

14. The one or more machine-readable storage media of claim 8, wherein the fabric memory controller is further to facilitate access to the node memory by the other nodes while the CPU is in a failed state.

15. A method comprising:

establishing, in a node memory of the node, and address map, wherein the node address map includes (i) a shared memory region that is mapped to a global memory shared between the node and other nodes, (ii) a reflected memory region that forms a portion of the global memory and is mapped to a space of the node memory that is not cacheable, and (iii) a semaphore region to provide a hardware assist for enforced data coherency of the global memory; and

managing, by a fabric memory controller of the node, access to the node memory by the other nodes.

16. The method of claim 15, wherein the semaphore region comprises a directory for each shared block of memory of the global memory.

17. The method of claim 16, further comprising:

receiving, from another node of the other nodes, a request for a lock associated with requested data stored in the share memory region;

granting, to the another node, the lock associated with the requested data based on the data contained in the directory; and

updating the directory in response to the grant of the lock.

18. The method of claim 17, wherein receiving the request for the lock comprises receiving a read request from the another node to an address in the directory.

19. The method of claim 18, wherein the read request includes an address offset and a type of the lock is defined by a value of the offset.

20. The method of claim 18, wherein to granting the lock comprises to transmitting an identifier of a destination node at which the requested data is stored.