Memory controller, non-volatile memory system, and method of operating the same

• US 10,296,453 B2
• Filed: 08/15/2016
• Issued: 05/21/2019
• Est. Priority Date: 09/22/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Jae-Sung
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Edouard, Jean C
• Application Number:
  US15/236,501
• Publication Number:
  US 20170083436A1
• Time in Patent Office: 1,009 Days
• Field of Search: 711103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control

Abstract

Provided are a memory controller, a non-volatile memory system, and a method of operating the same. A method of operating a memory system includes selecting a plurality of source blocks to be garbage-collected, copying selected valid data from two or more source blocks among the plurality of source blocks into a destination block, storing changed mapping information in an update cache according to a result of the copying, and updating a mapping table by using the mapping information stored in the update cache.

Claims

1. A method of performing a garbage collection operation in a memory system including a memory controller that includes an update cache and a non-volatile memory device that includes a memory cell array having a storage region divided into blocks and a meta region storing mapping tables for managing data stored in the storage region, the method comprising:

storing mapping information in the update cache;

determining, by the memory controller, whether to perform a sequential garbage collection operation or a simultaneous garbage collection operation for at least one of the blocks;

upon determining to perform the sequential garbage collection operation, collecting valid data from one source block among the blocks, and updating the mapping information stored in the update cache in response to collecting the valid data from the one source block, else

upon determining to perform the simultaneous garbage collection operation, simultaneously collecting valid data from a plurality of source blocks among the blocks, and updating the mapping information stored in the update cache in response to collecting the valid data from the plurality of source blocks.

2. The method of claim 1, wherein the determining of whether to perform a sequential garbage collection operation or simultaneous garbage collection operation for the at least one of the blocks comprises determining, for at least one of the blocks, whether data stored in the at least one of the blocks is random data, and if the data stored in the at least one of the blocks is random data, determining to perform the simultaneous garbage collection operation, else determining to perform the sequential garbage collection operation.

3. The method of claim 1, wherein the determining of whether to perform a sequential garbage collection operation or simultaneous garbage collection operation for the at least one of the blocks comprises:

determining a valid data ratio for data stored in at least one of the blocks;

comparing the determined valid data ratio to a valid data ratio threshold; and

upon determining that the determined valid data ratio is greater than or equal to the valid data ratio threshold, determining to perform the simultaneous garbage collection operation, else determining to perform the sequential garbage collection operation.

4. The method of claim 1, wherein the determining of whether to perform a sequential garbage collection operation or simultaneous garbage collection operation for the at least one of the blocks comprises:

(a) determining for at least one of the blocks whether data stored in the at least one of the blocks is random data; and

(b) determining a valid data ratio for data stored in at least one of the blocks and comparing the determined valid data ratio to a valid data ratio threshold,

such that the determining of whether to perform the simultaneous garbage collection operation or the sequential garbage collection operation is made in response to at least one of (a) and (b).

5. The method of claim 1, further comprising:

after updating the mapping information stored in the update cache in response to the collecting of valid data from the one source block, updating at least one of the mapping tables stored in the meta region of the memory cell array using the updated mapping information stored in the update cache.

6. The method of claim 1, further comprising:

after updating the mapping information stored in the update cache in response to the collecting of valid data from the plurality of source blocks, updating at least one of the mapping tables stored in the meta region of the memory cell array using the updated mapping information stored in the update cache.

7. The method of claim 1, further comprising:

upon determining to perform the simultaneous garbage collection operation, selecting at least two of the blocks as selected source blocks and selecting at least one of the blocks as a destination block,

wherein the simultaneously collecting the valid data from the plurality of source blocks comprises simultaneously copying valid data from the source blocks to the destination block.

8. The method of claim 7, wherein the mapping tables stored in the meta region of the memory cell array include a first mapping table and a second mapping table, the selected source blocks include a first source block and a second source block, and the simultaneous copying of valid data from the selected source blocks comprises:

identifying first valid data stored in the first source block and associated with the first mapping table;

identifying second valid data stored in the second source block and associated with the first mapping table; and

simultaneously copying the first valid data from the first source block and second valid data from the second source block.

9. The method of claim 8, further comprising:

updating the mapping information stored in the update cache associated with the first mapping table in response to the simultaneously copying of the first valid data from the first source block and the second valid data from the second source block; and

updating the first mapping table in the meta region of the memory cell array using the updated mapping information stored in the update cache.

10. The method of claim 9, wherein the updating of the first mapping table in the meta region of the memory cell array is performed in response to an update timing schedule.

11. A memory controller that controls operation of a memory device that includes a memory cell array having a meta region storing mapping tables and a storage region divided into blocks, the memory controller comprising:

a source block property determining unit that references mapping information to determine a property of valid data stored in the blocks and generate a determination result;

a source selecting block unit that, responsive to the determination result, identifies at least two selected source blocks suitable for use during a simultaneous garbage collection operation and generates a selection result;

a garbage collection performing unit that, responsive to the selection result, controls execution of the simultaneous garbage collection operation by garbage collecting simultaneously from the selected source blocks; and

an update cache that stores initial mapping information received from the memory device and updates the initial mapping information in response to the execution of the simultaneous garbage collection operation to generate and store updated mapping information.

12. The memory controller of claim 11, wherein the update cache is a volatile memory.

13. The memory controller of claim 11, wherein the memory device is a solid-state drive (SSD).

14. The memory controller of claim 13, wherein the memory cell array is a three-dimensional flash memory cell array.

15. The memory controller of claim 11, wherein the source block property determining unit, source block selecting unit, and garbage collection performing unit are implemented as at least one of software stored in a non-volatile memory and firmware implementing at least in part a flash translation layer.

16. The memory controller of claim 11, wherein the property of valid data determined by the source block property determining unit includes at least one of;

randomness of storage for the valid data, relationship of the valid data to at least one of the mapping tables, and storage location of the valid data in the storage region.