Failure logic modeling method for a high-speed railway train operation control on-board system

• US 10,296,685 B2
• Filed: 04/24/2014
• Issued: 05/21/2019
• Est. Priority Date: 03/27/2014
• Status: Expired due to Fees

• Current Assignee: Beijing Jiaotong University
• Original Assignee: Beijing Jiaotong University
• Inventors: Zheng, Wei, Yang, Lingyun, Kong, Weijie, Ren, Dewang, Wang, Lixiang
• Primary Examiner(s): Phan, Thai Q
• Application Number:
  US14/909,853
• Publication Number:
  US 20170124234A1
• Time in Patent Office: 1,853 Days
• Field of Search: 703 2, 703 6, 700 90, 701 291, 701 294, 701 296
• CPC Class Codes: B61L 27/20 Trackside control of safe travel of vehicle or train, e.g. braking curve calculation
• CPC Class Codes: B61L 27/60 Testing or simulation
• CPC Class Codes: G06F 30/15 Vehicle, aircraft or watercraft design
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

The present invention provides a failure logic modeling method for a high-speed railway train operation control on-board system, including the following steps: determining the functional relationship between the structure and the parts of the train control on-board system; analyzing the failures of the parts based on known failures of the train control on-board system in combination with brainstorming; establishing an FMEA table to generalize the failures of the parts; editing and simulating the failures by using a modeling tool. By adopting the present invention, the failure modes analyzed are more systematic, and the failure logic modeling can be carried out from a global perspective more easily, the whole process can be better targeted meanwhile, the security analysis complexity of the train control system will be effectively reduced and the development period of the train control system will be shortened.

Claims

1. A failure logic modeling method for a high-speed railway train operation control on-board system comprising modules and components, the method comprising steps of:

determining the functional relationship between the modules and components of the train control on-board system;

analyzing the modules and components to identify failures and failure modes based in part on results of the determining step and on known failures of the train control on-board system accessed from a database;

generating an FMEA table to associate, for each module and component for which a failure was identified, at least one of the failure modes; and

modeling and simulating the failures using a modeling tool.

2. The method of claim 1, wherein the step of determining the functional relationship between the modules and components of the train control on-board system further comprises a step of:

determining the structure of the train control on-board system to clarify the functional relationship between the modules and the components according to a general technical solution of the high-speed railway train control system, a structure diagram of the train control on-board system and a UML model of the system.

3. The method of claim 1, wherein the step of analyzing the modules and components to identify failures and failure modes based in part on results of the determining step and on known failures of the train control on-board system accessed from a database further comprises a step of:

matching corresponding guide words with parameters in an information flow, generating a sequence of failures, and analyzing the reason and result of each failure;

wherein the database comprises a risk database.

4. The method of claim 1, wherein the step of generating an FMEA table to associate, for each module and component for which a failure was identified, at least one failure mode further comprises steps of:

carrying out sub-module division on the train control on-board system according to actual demands;

listing the failure modes of the modules and the components of the train control on-board system through the FMEA table;

arranging the failure components from bottom to top for analysis and summarization;

analyzing every input failure, self-failure, output failure and double failure of each component, and sequentially transmitting the failures until the failures arrive at a top end ATPCU.

5. The method of claim 4, wherein the FMEA table comprises a failure component, an input component, an input failure mode, a self-failure mode, an output failure mode, a double failure mode and an output component.

6. The method of claim 1, wherein the step of modeling the failures using a modeling tool further comprises a step of:

modeling, using failure logic models, summarized failure modes and the structural relationships between the modules and the components, and generating system level and component level failure logic models in combination with a simulation technology and according to train control on-board system design.

7. The method of claim 6, wherein the failure logic models comprise a balise, a miniature antenna unit CAU, a balise transmission module BTM, a radio communication station GSM-R, a general confidentiality device GCD, an on-board security transmission unit STU, a secure digital input output VDX, a radar, a speed sensor, a speed and distance measurement unit SDU, a speed and distance processing unit SDP, a man-machine interface DMI and an on-board security computer unit ATPCU.

8. The method of claim 1, wherein in the step of modeling and simulating the failures using a modeling tool, a stateflow modeling tool is used.

9. The method of claim 1, wherein the step of modeling and simulating the failures using a modeling tool further comprises steps of:

modeling a transmission process of an input failure and a self-failure in a failure component using a stateflow component model, outputting the output failure to simulink through stateflow, and obtaining a transmission result of the failures in a display device of the simulink;

establishing an overall architecture of the failure logic model and a failure transmission relationship of the modules in a Matlab/simulink component;

changing the self-failure and the input failure of a bottom layer module in a simulink component, and indicating whether the failure happens via a Boolean value generated in a switch form;

establishing an event-driven model in a stateflow component, wherein the driving conditions are the input failure and the self-failure in the external simulink component; and

transferring a bottom failure layer into the ATPCU, and setting the display device at the output end of the ATPCU to obtain a final simulation result.