Semiconductor devices, and related control logic assemblies, control logic devices, electronic systems, and methods

• US 10,297,290 B1
• Filed: 12/29/2017
• Issued: 05/21/2019
• Est. Priority Date: 12/29/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beigel, Kurt D., Sills, Scott E.
• Primary Examiner(s): Norman, James G
• Application Number:
  US15/858,188
• Time in Patent Office: 508 Days
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/10 : Phase change RAM [PCRAM, PRAM] devices
• CPC Class Codes: H10B 63/34 : of the vertical channel field-effect transistor type

Abstract

A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.

Claims

1. A control logic device, comprising:

a vertical transistor comprising;

a semiconductive structure comprising a source region, a drain region, and a channel region between the source region and the drain region; and

a shared gate electrode;

another vertical transistor comprising;

another semiconductive structure comprising another source region, another drain region, and another channel region between the another source region and the another drain region; and

the shared gate electrode, the shared gate electrode laterally intervening between the channel region of the semiconductive structure and the another channel region of the another semiconductive structure; and

at least one additional vertical transistor neighboring the another vertical transistor and comprising;

at least one additional semiconductive structure comprising an additional source region, an additional drain region, and an additional channel region vertically between the additional source region and the additional drain region; and

an additional shared gate, the additional shared gate laterally intervening between the another channel region of the another semiconductive structure and the at least one additional channel region of the at least one additional semiconductive structure;

wherein the semiconductive structure of the vertical transistor, the another semiconductive structure of the another vertical transistor, and the at least one additional semiconductive structure of the at least one additional vertical transistor are not all substantially aligned with one another in a single lateral direction.

2. The control logic device of claim 1, wherein:

the semiconductive structure of the vertical transistor comprises an N-type source region, an N-type drain region, and a P-type channel region vertically between the N-type source region and the N-type drain region; and

the another semiconductive structure of the another vertical transistor comprises a P-type source region, a P-type drain region, and an N-type channel region vertically between the P-type source region and the P-type drain region.

3. The control logic device of claim 1, wherein:

the semiconductive structure of the vertical transistor comprises a P-type source region, a P-type drain region, and an N-type channel region vertically between the P-type source region and the P-type drain region; and

the another semiconductive structure of the another vertical transistor comprising an additional P-type source region, an additional P-type drain region, and an additional N-type channel region vertically between the additional P-type source region and the additional P-type drain region.

4. The control logic device of claim 1, wherein:

the semiconductive structure of the vertical transistor comprises a semiconductive pillar comprising the source region, the drain region, and the channel region vertically between the source region and the drain region; and

the another semiconductive structure of the another vertical transistor comprises another semiconductive pillar comprising the another source region, the another drain region, and the another channel region vertically between the another source region and the another drain region.