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Magnetic storage cell memory with back hop-prevention

  • US 10,297,302 B2
  • Filed: 12/06/2016
  • Issued: 05/21/2019
  • Est. Priority Date: 06/26/2015
  • Status: Active Grant
First Claim
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1. A memory implemented on a semiconductor chip, comprising:

  • circuitry to implement a write operation, the circuitry to write data into a location within a memory cell array of the memory, the location specified by a write address of the write operation, the circuitry comprising a) and b) below;

    a) first circuitry to compare the data with a version of the data that was previously written at the location during a prior iteration of the write operation;

    b) second circuitry to re-write into the memory cell array those bits of the version of the data that, from the comparison, do not match the data.

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