Magnetic storage cell memory with back hop-prevention

• US 10,297,302 B2
• Filed: 12/06/2016
• Issued: 05/21/2019
• Est. Priority Date: 06/26/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Augustine, Charles, Tomishima, Shigeki, Wu, Wei, Lu, Shih-Lien, Tschanz, James W., Panagopoulos, Georgios, Naeimi, Helia
• Primary Examiner(s): Hidalgo, Fernando
• Application Number:
  US15/371,122
• Publication Number:
  US 20170178708A1
• Time in Patent Office: 896 Days
• Field of Search: 365 46, 365 55, 365 74, 365 97, 365100, 365131, 365148, 365158, 365171, 365173, 365163
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits

Abstract

An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Claims

1. A memory implemented on a semiconductor chip, comprising:

circuitry to implement a write operation, the circuitry to write data into a location within a memory cell array of the memory, the location specified by a write address of the write operation, the circuitry comprising a) and b) below;

a) first circuitry to compare the data with a version of the data that was previously written at the location during a prior iteration of the write operation;

b) second circuitry to re-write into the memory cell array those bits of the version of the data that, from the comparison, do not match the data.

2. The memory of claim 1 wherein the memory cell array is a resistive memory cell array.

3. The memory of claim 2 wherein the re-write is performed with a stronger drive current than the previous write of the version of the data.

4. The memory of claim 3 wherein the second circuitry is to iteratively compare previously written versions of the data against a correct value and re-write those bits of the previously written versions that do not match their correct data.

5. The memory of claim 4 wherein each re-write is characterized by a stronger drive current.

6. The memory of claim 3 wherein the stronger drive current is effected with at least one of:

a) increased write current amplitude;

b) increased write time.

7. The memory of claim 1 wherein the re-write is performed with a stronger drive current than the previous write of the version of the data.

8. The memory of claim 1 wherein the second circuitry is to iteratively compare previously written versions of the data against a correct value and rewrite those bits of the previously written versions that do not match their correct data.

9. The memory of claim 1 wherein each re-write is characterized by a stronger drive current.

10. The memory of claim 9 wherein the stronger drive current is effected with at least one of:

a) increased write current amplitude;

b) increased write time.

11. A computing system, comprising:

a plurality of processing cores; and

,

circuitry to implement a write operation, the circuitry to write data into a location within a memory cell array of the memory, the location specified by a write address of the write operation, the circuitry comprising a) and b) below;

a) first circuitry to compare the data with a version of the data that was previously written at the location during a prior iteration of the write operation;

b) second circuitry to re-write into the memory cell array those bits of the version of the data that, from the comparison, do not match the data.

12. The computing system of claim 11 wherein the memory cell array is a resistive memory cell array.

13. The computing system of claim 12 wherein the re-write is performed with a stronger drive current than the write.

14. The computing system of claim 13 wherein the second circuitry is to iteratively compare previously written versions of the data against a correct value and rewrite those bits of the previously written versions of the data that do not match their correct data.

15. The computing system of claim 14 wherein each re-write is characterized by a stronger drive current.

16. The computing system of claim 13 wherein the stronger drive current is effected with at least one of:

a) increased write current amplitude;

b) increased write time.

17. The computing system of claim 11 wherein the re-write is performed with a stronger drive current than the previous write of the version of the data.

18. The computing system of claim 11 wherein the second circuitry is to iteratively compare previously written versions of the data against a correct value and rewrite those bits of the previous versions of the data that do not match their correct data.

19. The computing system of claim 11 wherein each re-write is characterized by a stronger drive current.

20. The computing system of claim 19 wherein the stronger drive current is effected with at least one of:

a) increased write current amplitude;

b) increased write time.