Stress relieving semiconductor layer

• US 10,297,460 B2
• Filed: 04/25/2017
• Issued: 05/21/2019
• Est. Priority Date: 05/01/2013
• Status: Active Grant

• Current Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Inventors: Shatalov, Maxim S., Yang, Jinwei, Sun, Wenhong, Jain, Rakesh, Shur, Michael, Gaska, Remigijus
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US15/496,887
• Publication Number:
  US 20170229611A1
• Time in Patent Office: 756 Days
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 29/158 Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66075 of devices having semiconductor bodies comprising group 14 or group 13/15 materials comprising semiconducting carbon H01L29/66015; comprising crystalline silicon carbide H01L29/66053
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer

Abstract

A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

Claims

1. A structure comprising:

a cavity containing layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers; and

a semiconductor layer immediately adjacent to the cavity containing layer, wherein a molar fraction of a semiconductor element in the semiconductor layer differs from a molar fraction of the semiconductor element in the cavity containing layer by at least two percent.

2. The structure of claim 1, further comprising:

a substrate; and

a nucleation layer located on the substrate, wherein the nucleation layer has a thickness of at least one nanometer, and wherein the cavity containing layer is located directly on the nucleation layer.

3. The structure of claim 2, wherein a surface of the substrate adjacent to the nucleation layer is inclined at an angle.

4. The structure of claim 3, wherein the angle is equal to or greater than 0.6 degrees and equal to or less than 3 degrees.

5. The structure of claim 2, wherein a surface of the substrate adjacent to the nucleation layer is patterned to include a plurality of regions, wherein each region corresponds to an etched area of the substrate having a different height than each immediately adjacent etched area of the substrate.

6. The structure of claim 5, wherein the plurality of regions are ordered so that the surface of the substrate declines towards a center of the substrate.

7. The structure of claim 3, wherein the surface of the substrate includes a plurality of atomic steps and a plurality of bunched steps.

8. The structure of claim 3, wherein the surface of the substrate includes a plurality of inclined surface sections.

9. The structure of claim 2, wherein the semiconductor layer is formed of a plurality of layers, wherein a first layer of the plurality of layers includes one of:

a tensile or a compressive stress and a second layer of the plurality of layers includes one of;

a tensile or a compressive stress that is opposite of the first layer.

10. The structure of claim 9, wherein the first layer includes a first molar ratio of group V precursors to group III precursors and the second layer includes a second molar ratio of group V precursors to group III precursors different from the first molar ratio, and a difference between the first molar ratio and the second molar is at least ten percent.

11. The structure of claim 9, wherein the first layer comprises Al_xGa_1-xN and the second layer comprises Al_yGa_1-yN, where x and y differ by at least five percent.

12. A device comprising:

an aluminum nitride nucleation layer, wherein the nucleation layer has a thickness of at least one nanometer and comprises a plurality of nucleation islands;

a cavity containing layer located directly on the nucleation layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers; and

a semiconductor layer immediately adjacent to the cavity containing layer, wherein a molar fraction of a semiconductor element in the semiconductor layer differs from a molar fraction of the semiconductor element in the cavity containing layer by at least two percent.

13. The device of claim 12, further comprising a substrate immediately adjacent to the nucleation layer, wherein a surface of the substrate adjacent to the nucleation layer is inclined at an angle equal to or greater than 0.6 degrees and equal to or less than 30 degrees.

14. The device of claim 12, wherein the cavity containing layer comprises aluminum nitride.

15. The device of claim 12, wherein a surface of a substrate adjacent to the nucleation layer is patterned to include a plurality of regions, wherein each region corresponds to an etched area of the substrate having a different height than each immediately adjacent etched area of the substrate.

16. The device of claim 12, wherein the cavity containing layer has a thickness in a range of 1 micron to 10 micron.

17. The device of claim 12, wherein the semiconductor layer is formed of a plurality of layers, wherein a first layer includes one of:

a tensile or a compressive stress and a second layer includes one of;

a tensile or a compressive stress that is opposite of the first layer.

18. The device of claim 17, wherein the first layer includes a first molar ratio of group V precursors to group III precursors and the second layer includes a second molar ratio of group V precursors to group III precursors, and a difference between the first molar ratio and the second molar is at least ten percent.

19. A method comprising:

fabricating a semiconductor structure, wherein the fabricating includes;

growing an aluminum nitride nucleation layer on a substrate, wherein the nucleation layer has a thickness of at least one nanometer;

forming a cavity containing layer directly on the nucleation layer, wherein the cavity containing layer has a thickness greater than two monolayers and a plurality of cavities; and

forming a semiconductor layer directly on the cavity containing layer, wherein a molar fraction of a semiconductor element in the semiconductor layer differs from a molar fraction of the semiconductor element in cavity containing layer by at least two percent.

20. The method of claim 19, wherein the fabricating further comprises:

patterning a surface of the substrate, wherein the patterning includes;

masking a plurality of regions on the substrate; and

etching the substrate between the plurality of regions, such that the surface of the substrate is inclined at an angle that is equal to or greater than 0.6 degrees and equal to or less than 3 degrees.