3D IC architecture with interposer and interconnect structure for bonding dies

• US 10,297,550 B2
• Filed: 05/05/2010
• Issued: 05/21/2019
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hu, Hsien-Pin, Yu, Chen-Hua, Chen, Ming-Fa, Lin, Jing-Cheng, Lai, Jiun Ren, Lin, Yung-Chi
• Primary Examiner(s): Mai, Anh D
• Application Number:
  US12/774,558
• Publication Number:
  US 20110193221A1
• Time in Patent Office: 3,303 Days
• Field of Search: 257700, 257725, 257737, 257E23021, 257E23023, 257698
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/07 Structure, shape, material or disposition of the bonding areas after the connecting process
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Claims

1. A device comprising:

an interposer substantially free from integrated circuit devices, wherein the interposer comprises;

a substrate having a first side and a second side opposite to the first side;

a plurality of conductive through-substrate vias (TSVs) in the substrate, wherein the conductive TSVs protrude from the first side and the second side of the substrate;

a first interconnect structure overlying the first side of the substrate, the first interconnect structure comprising a first dielectric layer and a first redistribution line disposed within the first dielectric layer, at least a portion of the first dielectric layer being located between the first redistribution line and the substrate, wherein the first redistribution line is spaced apart from the first side of the substrate and physically contacts at least one of the plurality of conductive TSVs protruding from the first side of the substrate, wherein the first side of the substrate facing the first dielectric layer is free from conductive material formed thereon, wherein the at least one of the plurality of conductive TSVs is electrically isolated and spaced apart from the substrate and spaced apart from the first dielectric layer of the first interconnect structure by a sidewall dielectric layer, wherein the at least one of the plurality of conductive TSVs and the sidewall dielectric layer extend through the portion of the first dielectric layer being located between the first redistribution line and the substrate, and wherein an interface extends between the sidewall dielectric layer and the portion of the first dielectric layer being located between the first redistribution line and the substrate; and

a second interconnect structure overlying the second side of the substrate, the second interconnect structure comprising a second dielectric layer and a second redistribution line disposed within the second dielectric layer, wherein the second redistribution line is spaced apart from the second side of the substrate and physically contacts the at least one of the plurality of conductive TSVs protruding from the second side of the substrate, wherein the second side of the substrate facing the second dielectric layer is free from conductive material formed thereon, and wherein an interface between a sidewall of the second dielectric layer and a sidewall of the at least one of the plurality of conductive TSVs contacts a bottommost point of the sidewall dielectric layer, the interface between the sidewall of the second dielectric layer and the sidewall of the at least one of the plurality of conductive TSVs further extending continuously in a straight line in a cross-sectional view and in a direction perpendicular to the second side of the substrate from the bottommost point of the sidewall dielectric layer to the second redistribution line;

a first die bonded onto the first interconnect structure;

a second die bonded to the second interconnect structure through a first plurality of metal bumps over a first plurality of recessed under-bump metallurgy (UBM) layers;

an underfill material interposing the second interconnect structure and the second die, wherein an interface extends between the underfill material and the second dielectric layer, and wherein the first plurality of metal bumps extend from the underfill material through the interface into the second dielectric layer;

an encapsulating material over the second interconnect structure and the second die;

a first conductive via fully penetrating the encapsulating material and extending into the second interconnect structure, wherein the first conductive via is electrically coupled to the second interconnect structure; and

a third interconnect structure over the encapsulating material, wherein the third interconnect structure is electrically coupled to the first conductive via.

2. The device of claim 1, wherein:

the encapsulating material encircles the second die; and

a first bump is formed overlying the third interconnect structure, the first bump electrically coupled to the first conductive via.

3. The device of claim 2, wherein the first bump is formed directly over a portion of the second die.

4. The device of claim 2, further comprising:

a redistribution layer (RDL) in the third interconnect structure, wherein the RDL is electrically coupled to the first conductive via.

5. The device of claim 2, further comprising:

a second conductive via penetrating the encapsulating material and electrically coupled to the second interconnect structure;

a redistribution layer (RDL) in the third interconnect structure, wherein the RDL is electrically coupled to the first or the second conductive via; and

a second bump formed overlying the third interconnect structure and electrically coupled to the RDL.

6. The device of claim 5, wherein the second bump is formed above a portion of the second die.

7. The device of claim 1, wherein the first die is bonded onto a region of the first interconnect structure opposing the second die.

8. The device of claim 1, wherein the first redistribution line comprises a multi-level redistribution line.

9. The device of claim 1, wherein the first conductive via extends at least partially through the second dielectric layer of the second interconnect structure, wherein the first conductive via is separated from the first plurality of metal bumps and the first plurality of recessed UBM layers by the second dielectric layer and the encapsulating material, and wherein the first conductive via and at least one of the recessed UBM layers physically contact a first surface of the second redistribution line.

10. A device, comprising:

an interposer substantially free from integrated circuit devices having a first interconnect structure overlying a first side of a substrate, a second interconnect structure overlying a second side of the substrate, and a plurality of conductive through-substrate vias (TSVs) in the substrate, wherein the conductive TSVs protrude from the first side of the substrate and the second side of the substrate, and wherein the first interconnect structure is electrically coupled to at least one of the plurality of conductive TSVs and the second interconnect structure is electrically coupled to the at least one of the plurality of conductive TSVs;

a first die bonded onto the first interconnect structure;

a second die bonded to the second interconnect structure through a first plurality of metal bumps over a first plurality of recessed under-bump metallurgy (UBM) layers;

an underfill material formed between the second die and the second interconnect structure;

an encapsulating material overlying the second interconnect structure and the second die;

a first conductive via fully penetrating the encapsulating material and extending into a portion of the second interconnect structure, the first conductive via electrically coupled to the second interconnect structure;

a third interconnect structure overlying the encapsulating material and electrically coupled to the first conductive via; and

a first bump formed overlying the third interconnect structure and electrically coupled to the first conductive via, the first interconnect structure comprising a first dielectric layer and a first redistribution line disposed within the first dielectric layer, wherein the first redistribution line is spaced apart from the first side of the substrate by a portion of the first dielectric layer separating the first redistribution line from the substrate, wherein the first redistribution line physically contacts the at least one of the plurality of conductive TSVs protruding from the first side of the substrate, the second interconnect structure comprising a second dielectric layer and a second redistribution line disposed within the second dielectric layer, wherein the second redistribution line is spaced apart from the second side of the substrate and physically contacts the at least one of the plurality of conductive TSVs protruding from the second side of the substrate, wherein an interface between a sidewall of the second dielectric layer and a sidewall of the at least one of the plurality of conductive TSVs extends continuously in a straight line in a cross-sectional view and in a direction perpendicular to the second side of the substrate from a point level with the second side of the substrate to the second redistribution line, wherein the first side of the substrate facing the first dielectric layer and the second side of the substrate facing the second dielectric layer are free from conductive material formed directly thereon, wherein an interface extends between the underfill material and the second dielectric layer, and wherein the first plurality of metal bumps extend from the underfill material through the interface into the second dielectric layer.

11. The device of claim 10, wherein the encapsulating material comprises a molding compound.

12. The device of claim 10, further comprising a redistribution layer (RDL) in the third interconnect structure, wherein the RDL is electrically coupled to the first conductive via.

13. The device of claim 10, further comprising:

a second conductive via penetrating the encapsulating material and electrically coupled to the second interconnect structure;

a redistribution layer (RDL) in the third interconnect structure, wherein the RDL is electrically coupled to the first or the second conductive via; and

a second bump formed overlying the third interconnect structure and electrically coupled to the RDL.

14. The device of claim 13, wherein the second bump is formed above a portion of the second die.

15. A device, comprising:

an interposer comprising a substrate, wherein the interposer is substantially free from integrated circuit devices;

a first die bonded to a first interconnect structure of the interposer, wherein;

the first interconnect structure is over a first side of the substrate;

the first interconnect structure comprises a first dielectric layer, and a first redistribution line disposed within the first dielectric layer, the first redistribution line being physically isolated and set apart from the first side of the substrate by a portion of the first dielectric layer; and

the first side of the substrate faces the first dielectric layer;

a second die bonded to a second interconnect structure of the interposer, wherein;

the second interconnect structure is over a second side of the substrate;

the second interconnect structure comprises a second dielectric layer, and a second redistribution line disposed within the second dielectric layer;

the second side of the substrate faces the second dielectric layer;

the second side of the substrate is free from conductive material formed thereon;

the second die is bonded to the second interconnect structure through first bumps; and

an underfill material is interposed between the second die and the second dielectric layer of the second interconnect structure, an interface extending between the underfill material and the second dielectric layer of the second interconnect structure, the first bumps extending from the underfill material through the interface into the second dielectric layer of the second interconnect structure;

an encapsulating material over the second interconnect structure and the second die;

a plurality of conductive through-substrate vias (TSVs) disposed in the substrate, wherein;

the plurality of conductive TSVs protrude from both the first side of the substrate and the second side of the substrate, wherein a through-substrate dielectric layer surrounds a portion of at least one of the plurality of conductive TSVs and is coaxially aligned with the at least one of the plurality of conductive TSVs, the portion of the at least one of the plurality of conductive TSVs being physically isolated from the portion of the first dielectric layer by the through-substrate dielectric layer and being physically and electrically isolated from the substrate by the through-substrate dielectric layer;

the first interconnect structure is electrically coupled to the at least one of the plurality of conductive TSVs, the at least one of the plurality of conductive TSVs and the through-substrate dielectric layer extending through the portion of the first dielectric layer, an interface extending between the through-substrate dielectric layer and the portion of the first dielectric layer, the at least one of the plurality of conductive TSVs, the through-substrate dielectric layer, and the portion of the first dielectric layer physically contacting a first surface of the first redistribution line;

the second interconnect structure is electrically coupled to the at least one of the plurality of conductive TSVs;

the first redistribution line contacts the at least one of the plurality of conductive TSVs protruding from the first side of the substrate, wherein an interface between the through-substrate dielectric layer and the at least one of the plurality of conductive TSVs extends from the first redistribution line to the second side of the substrate and ends at a surface of the second dielectric layer facing the second side of the substrate; and

the second redistribution line is spaced apart from the second side of the substrate and contacts the at least one of the plurality of conductive TSVs protruding from the second side of the substrate;

a first conductive via penetrating the encapsulating material, wherein the first conductive via extends into a portion of the second interconnect structure and is electrically coupled to the second interconnect structure;

a third interconnect structure overlying the encapsulating material, wherein the third interconnect structure is electrically coupled to the first conductive via; and

a bump formed over the third interconnect structure, wherein the bump is electrically coupled to the first conductive via.

16. The device of claim 15, wherein the bump is laterally over a portion of the second die.

17. The device of claim 15, further comprising a third redistribution line in the third interconnect structure, wherein the third redistribution line is electrically coupled to the first conductive via.

18. The device of claim 15, further comprising:

a second conductive via penetrating the encapsulating material and electrically coupled to the second interconnect structure;

a third redistribution line in the third interconnect structure, wherein the third redistribution line is electrically coupled to the first or the second conductive via; and

a second bump overlying the third interconnect structure and electrically coupled to the third redistribution line.

19. The device of claim 18, wherein the second bump is formed over a portion of the second die.

20. The device of claim 15, wherein the encapsulating material encircles the second die.