Methods for processing a 3D semiconductor device
First Claim
1. A method for processing a 3D semiconductor device, the method comprising:
- providing a wafer comprising a plurality of first dies, said plurality of first dies comprising a first transistor layer and a first interconnection layer;
completing a step of transferring a plurality of second dies each overlaying at least one of said first dies,wherein each of said plurality of second dies comprises a second transistor layer,wherein at least one of said plurality of first dies is substantially larger in area than at least one of said plurality of second dies, andwherein each of said plurality of second dies has a thickness greater than six microns; and
completing a step of thinning said plurality of second dies,wherein each of said plurality of second dies has a thickness of less than 2 microns.
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Abstract
A method for processing a 3D semiconductor device, the method including: providing a wafer including a plurality of first dies, the plurality of first dies including a first transistor layer and a first interconnection layer; completing a step of transferring a plurality of second dies each overlaying at least one of the first dies, where each of the plurality of second dies includes a second transistor layer, where at least one of the plurality of first dies is substantially larger in area than at least one of the plurality of second dies, and where each of the plurality of second dies has a thickness greater than six microns; and completing a step of thinning the plurality of second dies, where each of the plurality of second dies has a thickness of less than 2 microns.
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Citations
20 Claims
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1. A method for processing a 3D semiconductor device, the method comprising:
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providing a wafer comprising a plurality of first dies, said plurality of first dies comprising a first transistor layer and a first interconnection layer; completing a step of transferring a plurality of second dies each overlaying at least one of said first dies, wherein each of said plurality of second dies comprises a second transistor layer, wherein at least one of said plurality of first dies is substantially larger in area than at least one of said plurality of second dies, and wherein each of said plurality of second dies has a thickness greater than six microns; and completing a step of thinning said plurality of second dies, wherein each of said plurality of second dies has a thickness of less than 2 microns. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for processing a 3D semiconductor device, the method comprising:
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providing a wafer comprising a plurality of first dies, said plurality of first dies comprising a first transistor layer and a first interconnection layer; completing a step of transferring a plurality of second dies each overlaying at least one of said first dies, wherein each of said plurality of second dies comprises a second transistor layer, wherein at least one of said plurality of first dies is substantially larger in area than at least one of said plurality of second dies, wherein said wafer has a diameter larger than 150 mm, wherein said second die is smaller than 30 mm by 30 mm, and wherein each of said plurality of second dies has a thickness greater than six microns; and completing a step of thinning said plurality of second dies, wherein each of said plurality of second dies has a thickness of less than 2 microns. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method for processing a 3D semiconductor device, the method comprising:
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providing a wafer comprising a plurality of first dies, said plurality of first dies comprising a first transistor layer and a first interconnection layer; and completing a step of transferring a plurality of second dies each overlaying at least one of said first dies, wherein each of said plurality of second dies comprises a second transistor layer, wherein at least one of said plurality of first dies is substantially larger in area than at least one of said plurality of second dies, wherein each of said plurality of second dies has a thickness greater than six microns, and wherein said wafer comprises a plurality of designated cavities, said designated cavities are designed for assisting placement of said second dies. - View Dependent Claims (17, 18, 19, 20)
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Specification