High density MOSFET array with self-aligned contacts delimited by nitride-capped trench gate stacks and method
First Claim
1. A high density trench-gated MOSFET device comprising:
- a semiconductor substrate;
an epitaxial region overlaying the semiconductor substrate, a body region overlying the epitaxial region and a source region overlying the body region;
an array of active nitride-capped trench gate stacks (ANCTGS), with inter-ANCTGS separations, disposed above the semiconductor substrate and embedded vertically into the source region, the body region and the epitaxial region, wherein each ANCTGS comprises a stack of a polysilicon trench gate embedded in a gate oxide shell and a silicon nitride cap covering a top surface of the polysilicon trench gate, wherein portions of the silicon nitride cap disposed on the top surface of the polysilicon trench gate is separated from the polysilicon trench gate, and laterally extending over edges of the gate oxide shell whereby forming, together with the source region, the body region and the epitaxial region, a MOSFET array;
a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region whereby the patterned metal layer forms, with the MOSFET array, a plurality of self-aligned source and body contacts through the inter-ANCTGS separations, wherein the top surface of the polysilicon trench gate extending to both sides of the gate oxide shell is above a top surface of the source region; and
a gate pickup area comprising;
a pickup nitride-capped trench gate stack (PNCTGS) disposed above the semiconductor substrate and embedded vertically into the epitaxial region, wherein the PNCTGS comprises a stack of polysilicon trench gate embedded in a gate oxide shell, wherein the polysilicon trench gate of the PNCTGS is routed to join the polysilicon trench gate of each ANCTGS; and
a pair silicon nitride cap with a center gap laterally registered to the gate oxide shell, the pair silicon nitride cap covers, except for the center gap, the top surface of the polysilicon trench gate whereby the patterned metal layer forms, through the center gap, a self-aligned gate contact to the top surface of polysilicon trench gate;
wherein the patterned metal layer contacts a top surface of the pair silicon nitride cap;
wherein a bottom surface of the patterned dielectric region is directly attached to a pad oxide region atop the source region;
wherein a portion of the pad oxide region is beneath the silicon nitride cap;
wherein the patterned dielectric region and the pad oxide region are made of different materials;
wherein the patterned dielectric region is directly attached to the silicon nitride cap; and
wherein a top surface of the patterned dielectric region is directly attached to the patterned metal layer.
1 Assignment
0 Petitions
Accused Products
Abstract
A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.
-
Citations
14 Claims
-
1. A high density trench-gated MOSFET device comprising:
-
a semiconductor substrate; an epitaxial region overlaying the semiconductor substrate, a body region overlying the epitaxial region and a source region overlying the body region; an array of active nitride-capped trench gate stacks (ANCTGS), with inter-ANCTGS separations, disposed above the semiconductor substrate and embedded vertically into the source region, the body region and the epitaxial region, wherein each ANCTGS comprises a stack of a polysilicon trench gate embedded in a gate oxide shell and a silicon nitride cap covering a top surface of the polysilicon trench gate, wherein portions of the silicon nitride cap disposed on the top surface of the polysilicon trench gate is separated from the polysilicon trench gate, and laterally extending over edges of the gate oxide shell whereby forming, together with the source region, the body region and the epitaxial region, a MOSFET array; a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region whereby the patterned metal layer forms, with the MOSFET array, a plurality of self-aligned source and body contacts through the inter-ANCTGS separations, wherein the top surface of the polysilicon trench gate extending to both sides of the gate oxide shell is above a top surface of the source region; and a gate pickup area comprising; a pickup nitride-capped trench gate stack (PNCTGS) disposed above the semiconductor substrate and embedded vertically into the epitaxial region, wherein the PNCTGS comprises a stack of polysilicon trench gate embedded in a gate oxide shell, wherein the polysilicon trench gate of the PNCTGS is routed to join the polysilicon trench gate of each ANCTGS; and a pair silicon nitride cap with a center gap laterally registered to the gate oxide shell, the pair silicon nitride cap covers, except for the center gap, the top surface of the polysilicon trench gate whereby the patterned metal layer forms, through the center gap, a self-aligned gate contact to the top surface of polysilicon trench gate; wherein the patterned metal layer contacts a top surface of the pair silicon nitride cap; wherein a bottom surface of the patterned dielectric region is directly attached to a pad oxide region atop the source region; wherein a portion of the pad oxide region is beneath the silicon nitride cap; wherein the patterned dielectric region and the pad oxide region are made of different materials; wherein the patterned dielectric region is directly attached to the silicon nitride cap; and wherein a top surface of the patterned dielectric region is directly attached to the patterned metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
Specification