Gate top spacer for FinFET

• US 10,297,614 B2
• Filed: 08/09/2016
• Issued: 05/21/2019
• Est. Priority Date: 08/09/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Basker, Veeraraghavan S., Gluschenkov, Oleg, Mochizuki, Shogo, Reznicek, Alexander
• Primary Examiner(s): Trinh, Michael M
• Application Number:
  US15/232,482
• Publication Number:
  US 20180047754A1
• Time in Patent Office: 1,015 Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

The capacitance between gate structures and source/drain contacts of FinFET devices is reduced by the incorporation of inner spacers in the top portions of the gate structures. A replacement metal gate process used in the fabrication of such devices includes formation of the inner spacers following partial removal of dummy gate material. The remaining dummy gate material is then removed and replaced with gate dielectric and metal gate material.

Claims

1. A structure for a FinFET device, comprising:

a plurality of parallel semiconductor fins disposed on a substrate;

a pair of outer spacers disposed directly on at least one of the plurality of fins;

a pair of inner spacers between and adjoining the outer spacers,

an electrically conductive gate including an upper gate portion between the inner spacers and a lower gate portion extending laterally beneath the inner spacers and between the outer spacers; and

extension junctions formed in the at least one fin, wherein the extension junctions do not extend laterally beneath the outer spacers;

wherein the inner spacers separate the upper gate portion and the outer spacers; and

wherein the lower gate portion separates the inner spacers and the at least one of the plurality of fins.

2. The structure of claim 1, wherein inner surfaces of the inner spacers are substantially vertical, and wherein inner surfaces of the outer spacers are substantially vertical.

3. The structure of claim 1, wherein the upper gate portion has a smaller width dimension than the lower gate portion, and wherein the width dimension of the lower gate portion is greater than that of the upper gate portion by approximately a combined width of the pair of inner spacers.

4. The structure of claim 1, wherein the upper gate portion has a greater height dimension than the lower gate portion.

5. The structure of claim 1, wherein the inner spacers comprise a low-k dielectric material.

6. The structure of claim 5, wherein the inner spacers comprise a dielectric material having a dielectric constant less than 3.9.

7. The structure of claim 6, wherein the inner spacers comprise a dielectric material having a dielectric constant less than 3.0.

8. The structure of claim 6, wherein the outer spacers comprise a dielectric material having a dielectric constant greater than 3.9.

9. The structure of claim 5, further including a high-k gate dielectric layer between the upper and lower gate portions of the electrically conductive gate and the inner and outer spacers.

10. The structure of claim 9, wherein the gate dielectric layer comprises at least one dielectric metal oxide having a dielectric constant greater than 3.9.

11. The structure of claim 9, further including a barrier layer between the upper and lower gate portions of the electrically conductive gate and the high-k gate dielectric layer.

12. The structure of claim 1, further including a barrier layer between the upper and lower gate portions of the electrically conductive gate and the inner and outer spacers.

13. The structure of claim 1, further including a dielectric cap on the electrically conductive gate and extending between the inner spacers.

14. The structure of claim 1, wherein the structure is monolithic, and wherein the fins are monocrystalline.

15. The structure of claim 1, further comprising source/drain regions adjoining the outer spacers and disposed directly on the at least one fin, wherein the outer spacers are between the source/drain regions and separate the source/drain regions from the electrically conductive gate.

16. The structure of claim 15, further comprising an interlayer dielectric disposed on the source/drain regions but not disposed on or between the outer spacers.

17. The structure of claim 1, further comprising an electrically insulating layer between the at least one fin and the substrate, wherein the at least one fin separates the outer spacers from the electrically insulating layer.

18. The structure of claim 17, wherein the electrically insulating layer comprises a buried oxide layer.

19. A structure for a FinFET device, comprising:

a plurality of parallel semiconductor fins disposed on a substrate;

a pair of outer spacers disposed directly on at least one of the plurality of fins;

a pair of inner spacers between and adjoining the outer spacers;

an electrically conductive gate including an upper gate portion between the inner spacers and a lower gate portion extending laterally beneath the inner spacers and between the outer spacers; and

source/drain regions adjoining the outer spacers and disposed directly on the at least one fin, wherein the outer spacers are between the source/drain regions and separate the source/drain regions from the electrically conductive gate;

wherein the inner spacers separate the upper gate portion and the outer spacers;

wherein the lower gate portion separates the inner spacers and the at least one of the plurality of fins; and

wherein the at least one fin comprises a channel region which extends laterally beneath the outer spacers and which does not extend laterally beneath the source/drain regions.