Vertical transport fin field effect transistor with asymmetric channel profile

• US 10,297,668 B1
• Filed: 01/22/2018
• Issued: 05/21/2019
• Est. Priority Date: 01/22/2018
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lee, Choonghyun, Anderson, Brent A., Ok, Injo, Seo, Soon-Cheon
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US15/876,905
• Time in Patent Office: 484 Days
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.

Claims

1. A plurality of vertical fin field effect transistors, comprising:

a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate;

an isolation region between the first region and the second region;

a gate dielectric layer on the first vertical fin and the second vertical fin;

a first combined work function layer on a lower portion of the gate dielectric layer on the second vertical fin;

a second work function layer on an upper portion of the gate dielectric layer on the second vertical fin;

a second combined work function layer on a lower portion of the gate dielectric layer on the first vertical fin; and

a fourth work function layer on an upper portion of the gate dielectric layer on the first vertical fin.

2. The plurality of vertical fin field effect transistors of claim 1, further comprising a first bottom source/drain region on the first region of the substrate and a second bottom source/drain region on the second region of the substrate, wherein the first bottom source/drain region is doped with an n-type dopant, and the second bottom source/drain region is doped with a p-type dopant.

3. The plurality of vertical fin field effect transistors of claim 2, wherein the third and fourth work function layers each have a thickness in the range of about 1 nm to about 10 nm.

4. The plurality of vertical fin field effect transistors of claim 3, wherein the first and second work function layers each have a thickness in the range of about 1 nm to about 10 nm.

5. The plurality of vertical fin field effect transistors of claim 4, wherein the first and second work function layers are a different work function material from the third and fourth work function layers.

6. A plurality of vertical fin field effect transistors, comprising:

a first bottom source/drain region on a first region of a substrate and a second bottom source/drain region on a second region of the substrate with an isolation region between the first region and the second region;

a first vertical fin on the first region of the substrate and a second vertical fin on the second region of the substrate;

a gate dielectric layer on the first vertical fin and the second vertical fin;

a first combined work function layer on a lower portion of the gate dielectric layer on the second vertical fin;

a second work function layer on an upper portion of the gate dielectric layer on the second vertical fin;

a second combined work function layer on a lower portion of the gate dielectric layer on the first vertical fin; and

a fourth work function layer on an upper portion of the gate dielectric layer on the first vertical fin.

7. The plurality of vertical fin field effect transistors of claim 6, wherein the fourth work function layer covers about 10% to about 25% of the vertical fin height on the upper portion of the gate dielectric layer on the first vertical fin, and the second work function layer covers about 10% to about 25% of the vertical fin height on the upper portion of the gate dielectric layer on the second vertical fin.

8. The plurality of vertical fin field effect transistors of claim 7, further comprising the second combined work function layer on the second work function layer on the second vertical fin.

9. The plurality of vertical fin field effect transistors of claim 8, wherein the first and second work function layers are selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), and ruthenium (Ru), and the third and fourth work function layers are selected from the group consisting of titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium aluminum carbon nitride (TiAlCN), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum carbon nitride (TaAlCN), lanthanum (La) doped TiN, and lanthanum (La) doped TaN.

10. The plurality of vertical fin field effect transistors of claim 9, wherein the first bottom source/drain region is doped with an n-type dopant, and the second bottom source/drain region is doped with a p-type dopant.