Bidirectional power MOSFET structure with a cathode short structure

• US 10,297,684 B2
• Filed: 09/29/2017
• Issued: 05/21/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Saxena, Tanuj, Khemka, Vishnu K., Gupta, Raghu, Zitouni, Moaniss, Qin, Ganming
• Primary Examiner(s): Choi, Calvin Y
• Application Number:
  US15/720,097
• Publication Number:
  US 20190103484A1
• Time in Patent Office: 599 Days
• Field of Search: None
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.

Claims

1. A metal oxide silicon field effect transistor (MOSFET) device comprising:

a semiconductor substrate (101) having first and second opposing surfaces (102, 103);

a first region (118) in the semiconductor substrate adjacent to the first surface (102), the first surface adjacent to a drain contact (104);

a second region (113) in the semiconductor substrate adjacent to the second surface (103), the second surface adjacent to a source contact (105), the second region including a source-located cathode short region (116) the source-located cathode short region (116) being isolated from an insulated gate (117), the source-located cathode short region being of a same conductivity type as the semiconductor substrate;

a doped region (114) of a different conductivity type as the semiconductor substrate;

a third region (112) in the semiconductor substrate between the first region and the second region, the third region adjacent to a body contact (107); and

an insulated gate (117) adjacent to at least the first region and the third region.

2. The MOSFET device of claim 1, wherein the source-located cathode short region is covered by the source contact.

3. The MOSFET device of claim 1, further comprising:

a first highly-doped region (110) in the first region adjacent to the drain contact.

4. The MOSFET device of claim 1, further comprising:

a highly-doped region (115) adjacent to the body contact.

5. The MOSFET device of claim 1, wherein the first region includes a first drift region (111) that forms a N-P junction, the first drift region having a doping concentration below that of a remainder of the first region.

6. The MOSFET device of claim 1, further comprising:

a second highly-doped region (114) in the second region adjacent to the source contact.

7. The MOSFET device of claim 6, wherein the second region is positioned to isolate the second highly-doped region and the source-located cathode short region from the insulated gate and the body contact.

8. The MOSFET device of claim 6, wherein the second region includes a second drift region, and wherein the source-located cathode short region is surrounded by the second drift region.

9. The MOSFET device of claim 1, wherein the source-located cathode short region is positioned adjacent to the source contact.

10. The MOSFET device of claim 1, wherein the doped region is positioned adjacent to the source-located cathode short region and adjacent to the source contact.

11. The MOSFET device of claim 1, wherein the source contact is coupled to the device at an intersection of the source-located cathode short region and the doped region.