Scalable protection voltage generation

• US 10,298,119 B2
• Filed: 11/07/2017
• Issued: 05/21/2019
• Est. Priority Date: 11/20/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Bala, Phalguni, Advani, Hiten
• Primary Examiner(s): Hiltunen, Thomas J.
• Application Number:
  US15/806,023
• Publication Number:
  US 20180062506A1
• Time in Patent Office: 560 Days
• CPC Class Codes: H02M 1/0022 the disturbance parameters being input voltage fluctuations
• CPC Class Codes: H02M 3/06 using resistors or capacitors, e.g. potential divider

Abstract

According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.

Claims

1. A circuit comprising:

a bias generator circuit coupled to a first voltage node, a second voltage node, and a ground voltage node, the first voltage node being a first voltage signal and the second voltage node being a second voltage signal, the second voltage signal being a positive voltage and being greater than the first voltage signal, the bias generator circuit configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node; and

a voltage protection circuit between the first voltage node and a low voltage circuit, the voltage protection circuit coupled to the plurality of protection voltages at the first plurality of nodes, each of the plurality of protection voltages are substantially equal to the second voltage signal, the voltage protection circuit configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.

2. The circuit of claim 1, wherein the voltage protection circuit further comprises a plurality of cascode devices serially coupled between the first voltage node and the low voltage circuit, each of the cascode devices having a gate coupled to one of the plurality of protection voltages.

3. The circuit of claim 2, wherein each of the cascode devices is a low voltage n-type metal-oxide-semiconductor field-effect transistor (NMOS transistor).

4. The circuit of claim 1, wherein the low voltage circuit comprises a charging circuit, a discharging circuit, and a sense circuit, the charging circuit, the discharging circuit, and the sense circuit are configured to detect Universal Serial Bus (USB) device attachment and detachment to and from the first voltage node.

5. The circuit of claim 1, wherein the bias generator circuit comprises a resistor ladder and a plurality of generator stages, wherein each of the generator stages are configured to generate one of the plurality of protection voltages.

6. The circuit of claim 5, wherein each of the generator stages having a first input, a second input, and a third input, the first input coupled to a first voltage tap of the resistor ladder, and the second input coupled a second voltage tap of the resistor ladder.

7. The circuit of claim 6, wherein a first generator stage of the plurality of generator stages has the third input coupled to the second voltage node, and wherein a second generator stage of the plurality of generator stages has the third input coupled to an output of the first generator stage.

8. The circuit of claim 6, wherein each of the plurality of generator stages further comprise:

a first p-type metal-oxide-semiconductor field-effect transistor (PMOS transistor) having a source terminal coupled to the first voltage tap of the resistor ladder and a gate terminal coupled to a drain terminal of the first PMOS transistor; and

a second PMOS transistor having a drain terminal coupled to the drain terminal of the first PMOS transistor, a source terminal coupled to the third input, and a gate terminal coupled to the second voltage tap of the resistor ladder.

9. The circuit of claim 6, wherein each of the plurality of generator stages further comprise:

a first n-type metal-oxide-semiconductor field-effect transistor (NMOS transistor) having a drain terminal coupled to the first voltage tap of the resistor ladder and a gate terminal coupled to drain terminal of the first NMOS transistor; and

a first PMOS transistor having a drain terminal coupled to a source terminal of the first NMOS transistor, a source terminal coupled to the third input, and a gate terminal coupled to the second voltage tap of the resistor ladder.

10. The circuit of claim 6, wherein each of the plurality of generator stages further comprise:

a diode having an anode terminal coupled to the first voltage tap of the resistor ladder; and

a first PMOS transistor having a drain terminal coupled to a cathode terminal of the diode, a source terminal coupled to the third input, and a gate terminal coupled to the second voltage tap of the resistor ladder.

11. A method comprising:

dividing a first supply voltage into a first set of voltages;

generating a plurality of protection voltages, a first protection voltage of the plurality of protection voltages based on two of the first set of voltages and a second supply voltage, the other protection voltages of the plurality of the protection voltages each based on two of the first set of voltages and one of the other protection voltages of the plurality of protection voltages, each of the plurality of protection voltages based on a different two of the first set of voltages; and

generating a first low voltage from the first supply voltage based on the plurality of protection voltages.

12. The method of claim 11, wherein when the second supply voltage is greater than the first supply voltage, the plurality of protection voltages are substantially equal.

13. The method of claim 11, wherein the generating a first low voltage from the first supply voltage based on the plurality of protection voltages further comprises dropping the first supply voltage with a plurality of cascode devices serially connected between the first supply voltage and the first low voltage, each of the cascode devices being coupled to one of the plurality of protection voltages.

14. A circuit comprising:

a bias generator circuit coupled to a first power supply voltage, the bias generator circuit comprising bias voltage generators having inputs coupled to a first set of input voltages, the bias voltage generators configured to generate bias voltages at their outputs, wherein the bias generator circuit comprises;

a first bias voltage generator having a first input and a second input coupled to different voltages of the first set of input voltages, and a third input coupled to a second power supply voltage, the second power supply voltage being different than the first power supply voltage;

a second bias voltage generator having a first input and a second input coupled to different voltages of the first set of input voltages, and a third input coupled to an output of the first bias voltage generator, wherein the bias generator circuit is further configured that when the first power supply voltage is greater than the second power supply voltage, the bias voltage generated by the second bias voltage generator being greater than the bias voltage generated by the first bias voltage generator; and

a cascode ladder comprising cascode devices serially coupled between the first power supply voltage and a low voltage device, each of the cascode devices being coupled to one of the bias voltages.

15. The circuit of claim 14 further comprising:

a resistor ladder comprising resistors serially coupled between the first power supply voltage and a ground voltage, the voltages of the first set of input voltages being nodes between resistors of the resistor ladder.

16. The circuit of claim 15, wherein the resistor ladder comprises M number of resistors serially coupled between the first power supply voltage and the ground voltage, wherein the bias generator circuit comprises N number of bias voltage generators, wherein N−

1 of the bias voltage generators have an output coupled to an input of another bias voltage generator, wherein M=2N+1.

17. The circuit of claim 14 further comprising:

a third bias voltage generator having a first input and a second input coupled to different voltages of the first set of input voltages and a third input coupled to an output of the second bias voltage generator.

18. The circuit of claim 14, wherein each of the cascode devices comprises an n-type metal-oxide-semiconductor field-effect transistor (NMOS transistor).

19. The circuit of claim 14, wherein the bias generator circuit is further configured that when the first power supply voltage is less than the second power supply voltage, the bias voltages generated by the first and the second bias voltage generators are substantially equal.

20. The circuit of claim 19, wherein the bias voltages generated by the first and the second bias voltage generators are substantially equal to the second power supply voltage.