Method and apparatus for providing a joint error correction code for a combined data frame comprising first data of a first data channel and second data of a second data channel and sensor system

• US 10,298,271 B2
• Filed: 01/21/2016
• Issued: 05/21/2019
• Est. Priority Date: 02/03/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hammerschmidt, Dirk, Rasbornig, Friedrich, Scheibenzuber, Wolfgang, Scherr, Wolfgang, Zettler, Thomas
• Primary Examiner(s): Dorman, Christian M
• Application Number:
  US15/003,230
• Publication Number:
  US 20160226525A1
• Time in Patent Office: 1,216 Days
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/102 Error in check bits
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/136 Reed-Muller [RM] codes
• CPC Class Codes: H03M 13/155 Shortening or extension of codes
• CPC Class Codes: H03M 13/1555 Pipelined decoder implementations
• CPC Class Codes: H03M 13/1595 Parallel or block-wise remainder calculation
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/2903 Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2909 Product codes
• CPC Class Codes: H03M 13/2942 wherein a block of parity bits is computed only from combined information bits or only from parity bits, e.g. a second block of parity bits is computed from a first block of parity bits obtained by systematic encoding of a block of information bits, or a block of parity bits is obtained by an XOR combination of sub-blocks of information bits
• CPC Class Codes: H03M 13/353 Adaptation to the channel
• CPC Class Codes: H03M 13/611 Specific encoding aspects, e.g. encoding by means of decoding
• CPC Class Codes: H03M 13/6356 by repetition or insertion of dummy data, i.e. rate reduction
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0056 Systems characterized by the type of code used H04L1/08 takes precedence
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0064 : Concatenated codes
• CPC Class Codes: H04L 1/0076 : Distributed coding, e.g. network coding, involving channel coding coding in both space and time H04L1/0618; cooperative diversity H04B7/022
• CPC Class Codes: H04L 1/0077 : Cooperative coding

Abstract

An apparatus (100) for providing an joint error correction code (140) for a combined data frame (254) comprising first data (112) of a first data channel and second data (122) of a second data channel comprises a first error code generator (110) configured to provide, based on a linear code, information on a first error correction code (114a, 114b) using the first data (112). The apparatus further comprises a second error code generator (120) configured to provide, based on the linear code, information on a second error correction code (124) using the second data (122). The apparatus is configured to provide the joint error correction code (140) using the information on the first error correction code (114a, 114b) and the information on the second error correction code (124).

Claims

1. A method, comprising:

generating, by a first sensor of a device, first data;

generating, by a second sensor of the device, second data,

the first sensor and the second sensor providing independent sensor signals;

generating, by a first processor core associated with the first sensor and based on a linear code, a first error protection code using the first data and independent of the generation of the second data;

generating, by the first processor core associated with the first sensor, a first data frame comprising the first data, first dummy data, and the first error protection code,

a position of the first dummy data within the first data frame corresponding to a position of the second data within a second data frame;

generating, by a second processor core associated with the second sensor and based on the linear code, a second error protection code using the second data;

generating, by the second processor core associated with the second sensor, the second data frame comprising the second data, second dummy data, and the second error protection code,

a position of the second dummy data within the second data frame corresponding to a position of the first data within the first data frame; and

generating, by the second processor core associated with the second sensor a joint error protection code for a combined data frame using the first error protection code and the second error protection code.

2. The method of claim 1, wherein the linear code comprises at least one of:

a set of parity bits for different parts of the combined data frame,

a Hamming-Code,

a Low-Density-Parity-Check-Code,

a Reed-Muller-Code,

a Hadamard-Code, or

a cyclic code.

3. The method of claim 1, wherein generating the first data frame comprises:

distributing data bits of the first data to a first set of positions within the first data frame and distributing first predetermined data bits to a second set of positions within the first data frame as the first dummy data; and

wherein generating the second data frame comprises;

distributing data bits of the second data to a second set of positions within the second data frame and distributing second predetermined data bits to a first set of positions within the second data frame as the second dummy data.

4. The method of claim 1, wherein generating the joint error protection code comprises:

providing an X-OR combination of the first error protection code and the second error protection code.

5. The method of claim 1, wherein generating the first error protection code comprises:

using a first cyclic code generator to process the first data; and

wherein generating the joint error protection code comprises;

initializing a second cyclic code generator using the first error protection code; and

using the initialized second cyclic code generator to process the second data.

6. The method of claim 5, wherein a content of a multiplicity of registers within the first cyclic code generator after processing of the first data is used as the first error protection code, and

wherein initializing the second cyclic code generator comprises:

copying the content of the multiplicity of registers within the first cyclic code generator to corresponding registers of the second cyclic code generator.

7. The method of claim 1, further comprising:

providing the combined data frame by distributing data bits of the first data to a first set of positions within the combined data frame;

distributing data bits of the second data to a second set of positions within the combined data frame; and

distributing data bits of the joint error protection code to a third set of positions within the combined data frame.

8. The method of claim 1, wherein generating the first data frame further comprises at least one of:

appending a data ID to the first data, or

adding timer information to the first data.

9. An apparatus comprising:

a first sensor configured to generate first data;

a second sensor configured to generate second data,

the first sensor and the second sensor providing independent sensor signals;

a first error code generator, implemented in a first processor core of the apparatus, configured to;

generate, based on a linear code, a first error protection code using the first data and independent of the generation of the second data, and

generate a first data frame comprising the first data, first dummy data, and the first error protection code,

a position of the first dummy data within the first data frame corresponding to a position of the second data within a second data frame;

a second error code generator, implemented in a second processor core of the apparatus, configured to;

generate, based on the linear code, a second error protection code using the second data, and

generate the second data frame comprising the second data, second dummy data, and the second error protection code,

a position of the second dummy data within the second data frame corresponding to a position of the first data within the first data frame;

a code combiner, implemented in the second processor core, configured to combine the first error protection code and the second error protection code to provide a joint error protection code for a combined data frame; and

an output interface configured to provide the combined data frame,

the combined data frame comprising the first data, the second data, and the joint error protection code.

10. The apparatus of claim 9, further comprising at least one of:

a first data frame assembler configured to appending a data ID to the first data or add timer information to the first data, or

a second data frame assembler configured to appending a data ID to the second data or add timer information to the second data.

11. The apparatus of claim 9, further comprising:

a code checker, configured to determine, whether the joint error protection code represents the first data and the second data within the combined data frame.

12. The apparatus of claim 11, wherein the code checker is implemented within the first processor core.

13. The apparatus of claim 9, wherein the code combiner is further configured to:

provide an X-OR combination of the first error protection code and the second error protection code.

14. The apparatus of claim 9, further comprising:

a combined frame generation register configured to receive the first data at first set of positions within the combined data frame, the second data at a second set of positions within the combined data frame, and data bits of the joint error protection code at a third set of positions within the combined data frame.

15. The apparatus of claim 9, wherein the code combiner is further configured to:

send the combined data frame to the first processor core for a check operation.

16. The apparatus of claim 9, further comprising:

an evaluator, implemented in the first processor core, configured to check whether information of the combined data frame has been modified during assembly or generation of the combined data frame.

17. A sensor system, comprising:

a first sensor circuit, including a first sensor, generating first data;

a second sensor circuit, including a second sensor, generating second data,

the first sensor and the second sensor providing independent sensor signals;

an apparatus for providing a joint error protection code for a combined data frame, comprising;

a first error code generator, implemented in a first processor core of the sensor system, configured to;

generate, based on a linear code, a first error protection code using the first data and independent of the second data, and

generate a first data frame comprising the first data, first dummy data, and the first error protection code,

a position of the first dummy data within the first data frame corresponding to a position of the second data within a second data frame;

a second error code generator, implemented in a second processor core of the sensor system, configured to;

generate, based on the linear code, a second error protection code using the second data, and

generate the second data frame comprising the second data, second dummy data, and the second error protection code,

a position of the second dummy data within the second data frame corresponding to a position of the first data within the first data frame; and

a code combiner, implemented in the second processor core, configured to combine the first error protection code and the second error protection code to provide the joint error protection code; and

an output interface configured to provide the combined data frame,

the combined data frame comprising the first data, the second data, and the joint error protection code.

18. The sensor system of claim 17, wherein sensor signals provided by the first sensor and the second sensor are indicative of a same physical quantity.

19. The sensor system of claim 18, wherein the same physical quantity is a strength of a magnetic field or a mechanical strain.

20. The sensor system of claim 17, wherein the second error code generator, when generating the second error protection code, is configured to:

generate the second error protection code independent of the generation of the first data.