Wafer level packaging for MEMS device

• US 10,301,171 B1
• Filed: 11/13/2017
• Issued: 05/28/2019
• Est. Priority Date: 11/13/2017
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Singapore Pte. Ltd. (Vanguard International Semiconductor Corporation)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Chakravarty, Siddharth, Yelehanka, Pradeep, Poikayil Satheesh, Sharath Poikayil, Yik, Chun Hoe, Kumar, Rakesh, Rajasekaran, Natarajan
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US15/810,163
• Publication Number:
  US 20190144265A1
• Time in Patent Office: 561 Days
• Field of Search: 257414, 257415, 257416, 257418, 257692, 257751, 257E21499, 257E215, 257E21502, 257E21505, 257E21567, 257E23142, 257E27009, 257E29324, 438 50, 438 51, 438106, 438107, 438118, 438455
• CPC Class Codes: B81B 2201/038 Microengines and actuators not provided for in B81B2201/031 - B81B2201/037
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2207/09 Packages
• CPC Class Codes: B81B 3/00 Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes B81B5/00 takes precedence
• CPC Class Codes: B81B 3/0016 Arrangements for avoiding sticking of the flexible or moving parts not provided for in groups B81B3/0005 - B81B3/0013
• CPC Class Codes: B81B 7/00 Microstructural systems; Auxiliary parts of microstructural devices or systems
• CPC Class Codes: B81B 7/0041 maintaining a controlled atmosphere with techniques not provided for in B81B7/0038
• CPC Class Codes: B81B 7/0051 between the package lid and the substrate
• CPC Class Codes: B81B 7/0054 between other parts not provided for in B81B7/0048 - B81B7/0051
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 1/00325 for reducing stress inside of the package structure
• CPC Class Codes: B81C 1/00579 Avoid charge built-up
• CPC Class Codes: B81C 1/00984 Methods for avoiding stiction when the device is in use not provided for in groups B81C1/00968 - B81C1/00976
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/035 Soldering
• CPC Class Codes: B81C 2203/036 Fusion bonding
• CPC Class Codes: H01L 21/52 Mounting semiconductor bodies in containers
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure

Abstract

A microelectromechanical system (MEMS) device is disclosed. The MEMS device includes a device substrate with a top device surface and a bottom device surface having a MEMS component in a device region. A top device bond ring is disposed on the top device surface surrounding the device region and a bottom device bond ring is disposed on the bottom device surface surrounding the device region. A top cap with a top cap bond ring is bonded to the top device bond ring by a top eutectic bond and a bottom cap with a bottom cap bond ring is bonded to the bottom device bond ring by a bottom eutectic bond. The eutectic bonds encapsulate the MEMS device.

Claims

1. A microelectromechanical system (MEMS) device comprising:

a device substrate, the device substrate includes a device region with a MEMS component, the device substrate comprises a top device surface and a bottom device surface, wherein

the top device surface includes a top device bond ring surrounding the device region, and

the bottom device surface includes a bottom device bond ring surrounding the device region,

the device substrate comprises a surface substrate, a proof mass substrate, and a dielectric layer disposed between the surface substrate and proof mass substrate, wherein the surface substrate includes an isolation region extending to the dielectric layer and isolating the device region on the surface substrate;

a top cap with an outer top cap surface and an inner top cap surface, wherein the inner top cap surface comprises a top cap bond ring surrounding the device region, wherein the top cap bond ring is bonded to the top device bond ring to form a top eutectic bond; and

a bottom cap with an outer bottom cap surface and an inner bottom cap surface, wherein the inner bottom cap surface comprises a bottom cap bond ring surrounding the device region, wherein the bottom cap bond ring is bonded to the bottom device bond ring to form a bottom eutectic bond.

2. The device of claim 1 wherein:

one of the top device bond ring and the top cap bond ring comprises aluminum (Al);

other of the top device bond ring and the top cap bond ring comprises germanium (Ge), the top eutectic bond comprises a top Al—

Ge eutectic bond;

one of the bottom device bond ring and the bottom cap bond ring comprises aluminum (Al); and

other of the bottom device bond ring and the bottom cap bond ring comprises germanium (Ge), the bottom eutectic bond comprises a bottom Al—

Ge eutectic bond.

3. The device of claim 2 wherein:

the top device bond ring comprises Al;

the top cap bond ring comprises Ge;

the bottom device bond ring comprises Al; and

the bottom cap bond ring comprises Ge.

4. The device of claim 1 wherein the top device bond ring, the top cap bond ring, the bottom device bond ring and bottom cap bond ring comprise Al, Ge, gold (Au), tin (Sn), silicon (Si), indium (In), copper (Cu), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), titanium nitride (TiN) and chromium (Cr) or a combination thereof.

5. The device of claim 1 wherein the top device bond ring, the top cap bond ring, the bottom device bond ring and bottom cap bond ring comprise:

a single eutectic bondable layer;

or

multiple layers including one or more eutectic bondable layer.

6. The device of claim 5 wherein a eutectic bondable layer comprises Al, Ge, gold (Au), tin (Sn), silicon (Si), indium (In), copper (Cu), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), titanium nitride (TiN) and chromium (Cr) or a combination thereof.

7. A method for forming a MEMS device comprising:

providing a device wafer having a top device surface and a bottom device surface, wherein the device wafer is processed with a MEMS component in a device region of the device wafer, wherein

the top device surface includes a top device bond ring surrounding the device region, and

the bottom device surface includes a bottom device bond ring surrounding the device region,

the device wafer comprises a surface substrate, a proof mass substrate, and a dielectric layer disposed between the surface substrate and proof mass substrate, wherein the surface substrate includes an isolation region extending to the dielectric layer and isolating the device region on the surface substrate;

providing a top cap wafer with an outer top cap surface and an inner top cap surface, wherein the inner top cap surface comprises a top cap bond ring surrounding the device region;

providing a bottom cap wafer with an outer bottom cap surface and an inner bottom cap surface, wherein the inner bottom cap surface comprises a bottom cap bond ring surrounding the device region;

performing a top eutectic bonding process, the top eutectic bonding process forms a top eutectic bond between the top cap bond ring and the top device bond ring; and

performing a bottom eutectic bonding process, the bottom eutectic bonding process forms a bottom eutectic bond between the bottom cap bond ring and the bottom device bond ring.

8. The method of claim 7 wherein:

one of the top device bond ring and the top cap bond ring comprises aluminum (Al);

other of the top device bond ring and the top cap bond ring comprises germanium (Ge), the top eutectic bond comprises a top Al—

Ge eutectic bond;

one of the bottom device bond ring and the bottom cap bond ring comprises aluminum (Al); and

other of the bottom device bond ring and the bottom cap bond ring comprises germanium (Ge), the bottom eutectic bond comprises a bottom Al—

Ge eutectic bond.

9. The method of claim 8 wherein:

the top device bond ring comprises Al;

the top cap bond ring comprises Ge;

the bottom device bond ring comprises Al; and

the bottom cap bond ring comprises Ge.

10. The method of claim 7 wherein the top device bond ring, the top cap bond ring, the bottom device bond ring and bottom cap bond ring comprise Al, Ge, gold (Au), tin (Sn), silicon (Si), indium (In), copper (Cu), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), titanium nitride (TiN) and chromium (Cr) or a combination thereof.

11. The method of claim 7 wherein the device wafer comprises:

a surface silicon wafer having a surface wafer top surface and a surface wafer bonding surface;

a proof mass wafer having a proof mass wafer bottom surface and a proof mass wafer bonding surface, wherein at least the proof mass wafer bonding surface includes a bonding dielectric layer; and

performing fusion bonding to bond the surface wafer bonding surface to the bonding dielectric layer on the proof mass wafer bonding surface to form a bonded device wafer, wherein the surface wafer top surface serves as the top surface of the device wafer and the proof mass wafer bottom surface serves as the bottom surface of the device wafer.

12. The method of claim 11 wherein:

the device wafer comprises a plurality of MEMS devices, each MEMS device comprising a MEMS component in the device region and surrounded by a top device bond ring on a top device surface and surrounded by a bottom device bond ring on a bottom device surface;

the top cap wafer with an outer top cap surface and an inner top cap surface, wherein the top cap wafer comprises a plurality of top caps, each top cap comprising a top cap bond ring surrounding the device region;

providing a bottom cap wafer with an outer bottom cap surface and an inner bottom cap surface, wherein the bottom cap wafer comprises a plurality of bottom caps, each bottom cap comprising a bottom cap bond ring surrounding the device region;

performing a top eutectic bonding process, the top eutectic bonding process forms a top eutectic bond between the top cap bond rings and the top device bond rings of the plurality of MEMS devices and top caps; and

performing a bottom eutectic bonding process, the bottom eutectic bonding process forms a bottom eutectic bond between the bottom cap bond rings and the bottom device bond rings of the plurality of MEMS devices and bottom caps; and

dicing the wafer stack comprising the top cap wafer, device wafer and bottom cap wafer to singulate the MEMS devices.

13. The method of claim 7 wherein:

providing the device wafer comprises providing a surface wafer, a proof mass wafer and a bonding dielectric layer between the surface and proof mass wafers, the device wafer is partially processed to form an upper part of the MEMS component in the device region of the surface wafer;

performing the top eutectic bonding process to bond the top cap wafer to the device wafer;

processing the proof mass wafer to form the remaining portion of the MEMS component; and

performing the bottom eutectic bonding process to bond the bottom cap wafer to the device wafer.

14. The method of claim 7 wherein the top eutectic bonding process and the bottom eutectic bonding process are performed with low bonding pressure at a bonding temperature of about 300-450°

C.

15. The method of claim 14 wherein:

the top eutectic bonding process is performed prior to the bottom eutectic bonding process; and

the bottom eutectic bonding process is performed at a lower bonding temperature than the top eutectic bonding process.

16. A method for forming a MEMS device comprising:

providing a device wafer having a top device surface and a bottom device surface, wherein the device wafer is processed to form a plurality of MEMS devices, wherein

a MEMS device includes

a MEMS component in a device region of the device wafer,

a top device bond ring on the top device surface surrounding the device region, and

a bottom device bond ring on the bottom device surface surrounding the device region,

the device wafer comprises a surface substrate, a proof mass substrate, and a dielectric layer disposed between the surface substrate and proof mass substrate, wherein the surface substrate includes an isolation region extending to the dielectric layer and isolating the device region on the surface substrate;

providing a top cap wafer with an outer top cap surface and an inner top cap surface, the top cap wafer comprises a plurality of top caps, wherein a top cap includes a top cap bond ring on the inner top cap surface surrounding the device region;

providing a bottom cap wafer with an outer bottom cap surface and an inner bottom cap surface, the bottom cap wafer comprises a plurality of bottom caps, wherein a bottom cap includes a bottom cap bond ring on the inner bottom cap surface surrounding the device region;

performing a top eutectic bonding process, the top eutectic bonding process forms a top eutectic bond between the top cap bond rings of the top cap wafer and the top device bond rings of the device wafer; and

performing a bottom eutectic bonding process, the bottom eutectic bonding process forms a bottom eutectic bond between the bottom cap bond rings of the bottom cap wafer and the bottom device bond rings of the device wafer.

17. The method of claim 16 wherein the top device bond rings, the top cap bond rings, the bottom device bond rings and bottom cap bond rings comprise Al, Ge, gold (Au), tin (Sn), silicon (Si), indium (In), copper (Cu), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), titanium nitride (TiN) and chromium (Cr) or a combination thereof.

18. The method of claim 16 wherein the top eutectic bonding process and the bottom eutectic bonding process are performed with low bonding pressure at a bonding temperature of about 300-450°

C.

19. The method of claim 16 wherein:

the top device surface comprises a top device dielectric, the top device bond ring is disposed on the top device dielectric; and

the bottom device surface comprises a bottom device dielectric, the bottom device bond ring is disposed on the bottom device surface.