Semiconductor device, semiconductor system and method for operating semiconductor device
First Claim
1. A semiconductor device comprising:
- a first clock control circuit which controls a first child clock source to receive a clock signal from a parent clock source;
a first channel management circuit which transmits a first clock request to the first clock control circuit in response to a first intellectual property (IP) block clock request received from a first IP block;
a second clock control circuit which controls a second child clock source to receive the clock signal from the parent clock source;
a second channel management circuit which transmits a second clock request to the second clock control circuit in response to a second IP block clock request received from a second IP block; and
a power management unit (PMU) which transmits a power control command to the first channel management circuit and the second channel management circuit to control a power state of the first IP block and the second IP block,wherein the first channel management circuit transmits a third clock request to the second channel management circuit and the second channel management circuit transmits an acknowledgement of receipt of the third clock request to the first channel management circuit, to maintain a master-slave relationship.
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Abstract
A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a first clock control circuit which controls a first child clock source to receive a clock signal from a parent clock source; a first channel management circuit which transmits a first clock request to the first clock control circuit in response to a first intellectual property (IP) block clock request received from a first IP block; a second clock control circuit which controls a second child clock source to receive the clock signal from the parent clock source; a second channel management circuit which transmits a second clock request to the second clock control circuit in response to a second IP block clock request received from a second IP block; and a power management unit (PMU) which transmits a power control command to the first channel management circuit and the second channel management circuit to control a power state of the first IP block and the second IP block, wherein the first channel management circuit transmits a third clock request to the second channel management circuit and the second channel management circuit transmits an acknowledgement of receipt of the third clock request to the first channel management circuit, to maintain a master-slave relationship. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 18, 19, 20)
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11. A semiconductor device comprising:
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a first channel management circuit which controls output of a clock signal to a first intellectual property block (IP block); a second channel management circuit which receives a clock request from the first channel management circuit and controls output of a clock signal to a second IP block in accordance with the clock request; and a power management unit (PMU) which transmits a power control command to the first channel management circuit and the second channel management circuit to control power states of the first IP block and the second IP block. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification