Methods of forming hybrid socket structures for package interconnect applications and structures formed thereby

• US 10,303,225 B2
• Filed: 09/29/2017
• Issued: 05/28/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Aygun, Kemal, Zhang, Zhichao, Geyik, Cemil, Kaur, Guneet
• Primary Examiner(s): Ho, Tu-Tu V
• Application Number:
  US15/720,484
• Publication Number:
  US 20190101961A1
• Time in Patent Office: 606 Days
• Field of Search: 257686
• CPC Class Codes: G06F 1/185 Mounting of expansion boards
• CPC Class Codes: H01R 12/7076 for connection between PCB and component, e.g. display
• CPC Class Codes: H01R 12/716 Coupling device provided on the PCB
• CPC Class Codes: H01R 13/10 Sockets for co-operation with pins or blades
• CPC Class Codes: H01R 13/2442 with a single cantilevered beam
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/10325 Sockets, i.e. female type connectors comprising metallic connector elements integrated in, or bonded to a common dielectric support
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/4038 Through-connections; Vertical interconnect access [VIA] connections H05K3/403, H05K3/42 take precedence
• CPC Class Codes: H05K 7/1409 by lever-type mechanisms
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Methods/structures of forming package structures are described. Those methods/structures may include a conductive pin comprising: a cantilever beam portion physically coupled with a first side of a package substrate; a contact pin portion, wherein a terminal end of the contact pin portion is physically and electrically coupled to a board; a housing structure comprising a housing cavity, wherein the contact pin portion is disposed at least partially within the housing cavity; and a conductive material disposed on housing sides and/or adjacent a surface of the housing cavity. The placement of the conductive material is optimized to meet the requirements for either double data rate (DDR) and/or peripheral component interface express (PCIe) interfaces.

Claims

1. A microelectronic package socket structure comprising:

a conductive pin comprising;

a first portion, wherein the first portion comprises a cantilever beam, wherein the cantilever beam is physically coupled with a first side of a package substrate; and

a second portion, wherein the second portion comprises a contact pin, wherein a terminal end of the contact pin portion is physically and electrically coupled to a board, wherein the first portion and the second portion are in direct physical contact and are physically continuous with each other;

a housing structure, wherein the housing structure comprises a housing cavity, wherein the second portion of the conductive pin is within the housing cavity;

a solder ball directly on the terminal end of the contact pin portion, wherein the solder ball is at least partially within the housing cavity; and

a conductive material, wherein the conductive material is on a sidewall of the housing cavity.

2. The microelectronic package socket structure of claim 1, wherein the conductive material comprises one of a plated copper material or a conductive via.

3. The microelectronic package socket structure of claim 1 wherein the conductive material is on at least a portion of a sidewall of the housing structure.

4. The microelectronic package socket structure of claim 3 wherein the conductive material is on a first side of the housing structure, adjacent the first portion of the conductive pin.

5. The microelectronic package socket structure of claim 4 wherein the conductive material is on a second side of the housing structure, wherein the second side is opposite the first side of the housing structure.

6. The microelectronic package socket structure of claim 1 wherein the housing structure comprises a high permittivity, low dielectric loss material.

7. The microelectronic package socket structure of claim 1 wherein the housing structure comprises a liquid crystal polymer materials.

8. The microelectronic package socket structure of claim 1 wherein the socket comprises a peripheral component interconnect express (PCIe) socket, and the package substrate includes a dynamic data rate (DDR) memory die.

9. A method of forming a microelectronic package socket structure comprising:

providing a housing structure for a conductive pin, wherein the housing structure comprises a first side and an opposing second side, and wherein the housing structure comprises a housing cavity;

placing a contact pin portion of the conductive pin within the housing cavity,

wherein a terminal end of the contact pin is placed directly onto a solder ball,

wherein the solder ball is at least partially within the housing cavity; and

;

attaching a cantilever beam portion of the conductive pin to a package substrate, wherein the cantilever beam portion and the contact pin portion are in direct physical contact and are physically continuous with each other; and

forming a conductive material on at least one of a sidewall of the housing structure or a sidewall of the housing cavity.

10. The method of forming the microelectronic package socket structure of claim 9 wherein placing the terminal end of the contact pin directly on the solder ball further comprises placing the solder ball onto a board.

11. The method of forming the microelectronic package socket structure of claim 9 further comprising forming a conductive material on the first side of the housing structure.

12. The method of forming the microelectronic package socket structure of claim 9 further comprising forming a conductive material on the second side of the housing structure.

13. The method of forming the microelectronic package socket structure of claim 9 further comprising wherein the housing structure comprises a high permittivity, low loss dielectric material.

14. The method of forming the microelectronic package socket structure of claim 10 wherein a height of the housing structure is selected to reduce an impedance of the package structure.

15. The method of forming the microelectronic package socket structure of claim 9 wherein an additional housing cavity is adjacent the housing cavity, wherein the additional housing cavity comprises an additional conductive pin, and further comprising forming a conductive material on a sidewall of the additional housing cavity.

16. The method of forming the microelectronic package socket structure of claim 10, wherein the package substrate further comprises a DDR memory, and the socket comprises a PCIe socket.

17. A microelectronic system, comprising:

a package substrate comprising one or more die;

a socket structure physically and electrically coupled to the one or more die, wherein the socket structure comprises;

a conductive pin comprising;

a first portion, wherein the first portion comprises a cantilever beam, wherein the cantilever beam is physically coupled with a first side of a package substrate; and

a second portion, wherein the second portion comprises a contact pin, wherein a terminal end of the contact pin portion is physically and electrically coupled to a board, wherein the first portion and the second portion are in direct physical contact and are physically continuous with each other;

a housing structure, wherein the housing structure comprises a housing cavity, wherein the second portion of the conductive pin is within the housing cavity;

a solder ball, wherein the solder ball is directly on the terminal end of the contact pin portion, wherein the solder ball is at least partially within the housing cavity; and

a conductive material on a sidewall of the housing cavity.

18. The microelectronic system of claim 17 wherein the socket structure comprises a portion of a land grid array (LGA) socket.

19. The microelectronic system of claim 17 wherein the at least one die comprises a DDR memory die.

20. The microelectronic system of claim 17 wherein the system includes a PCIe interface.

21. The microelectronic system of claim 17 wherein the system includes a DDR interface.

22. The microelectronic system of claim 20 wherein the system comprises a high speed single ended interconnect.

23. The microelectronic system of claim 17 wherein the system comprises a differential ended interconnect.

24. The microelectronic system of claim 17 wherein the system is capable of providing data rates greater than about 2.0 GB/link.

25. The microelectronic package system of claim 24 wherein the conductive material comprises a conductive plated material, and wherein the solder ball is directly on the board.