Nonvolatile memory device and operation method thereof

• US 10,303,372 B2
• Filed: 12/01/2016
• Issued: 05/28/2019
• Est. Priority Date: 12/01/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Youngjin, Seo, Sungyong, Lim, Sun-Young, Kang, Uksong, Kim, Chankyung, Chang, Duckhyun, Choi, JinHyeok
• Primary Examiner(s): Peugh, Brian R
• Application Number:
  US15/366,137
• Publication Number:
  US 20170153826A1
• Time in Patent Office: 908 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/305 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/313 In storage device
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer

Abstract

A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

Claims

1. A nonvolatile memory device comprising:

a nonvolatile memory;

a volatile memory being a cache memory of the nonvolatile memory;

a first controller configured to control the nonvolatile memory; and

a second controller configured to;

receive a device write command and an address; and

transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the device write command and the address being received.

2. The nonvolatile memory device of claim 1, wherein the volatile memory is configured to, in response to the first read command and the address being transmitted, transmit, through a memory data line, first data that is stored in an area corresponding to a part of the address, of the volatile memory, and transmit, through a tag data line, a tag that is stored in the area.

3. The nonvolatile memory device of claim 2, wherein the first controller is further configured to:

receive the first data transmitted from the volatile memory through the memory data line;

receive the tag transmitted from the volatile memory through the tag data line; and

selectively store the first data that is received, in the nonvolatile memory based on the address and the tag that is received.

4. The nonvolatile memory device of claim 3, wherein the first controller is further configured to, in response to the tag that is received being different from the part of the address, store the first data that is received, in the nonvolatile memory.

5. The nonvolatile memory device of claim 1, wherein each of the volatile memory and the first controller is further configured to receive write data from an external device,

wherein the volatile memory is configured to store the write data in a first area corresponding to the address, of the volatile memory, in response to the first write command and the address being transmitted, and

wherein the first controller is further configured to store the write data in a second area corresponding to the address, of the nonvolatile memory, in response to the second write command and the address being transmitted.

6. The nonvolatile memory device of claim 5, wherein the second controller is further configured to transmit, to the volatile memory, a write tag corresponding to the write data, and

wherein the volatile memory is further configured to store both the write data and the write tag in a third area corresponding to a part of the address, of the volatile memory.

7. The nonvolatile memory device of claim 5, wherein the write data is received from the external device through a memory data line after a time period elapses from a point in time when the device write command and the address are received from the external device.

8. The nonvolatile memory device of claim 7, further comprising a serial presence detect chip configured to transmit, to the external device, information of the time period.

9. The nonvolatile memory device of claim 1, further comprising a data buffer connected to an external device and configured to:

share a memory data line with the volatile memory and the first controller; and

operate based on a control of the second controller.

10. The nonvolatile memory device of claim 1, wherein the volatile memory is a direct mapping cache memory of the nonvolatile memory.

11. A nonvolatile memory device comprising:

a nonvolatile memory;

a volatile memory being a cache memory of the nonvolatile memory;

a first controller configured to control the nonvolatile memory; and

a second controller configured to;

receive a first device read command and an address; and

transmit a first read command and the address to the volatile memory through a first bus, and transmit a second read command and the address to the first controller through a second bus, in response to the first device read command and the address being received,

wherein the volatile memory is configured to, in response to the first read command and the address being transmitted, transmit, through a memory data line, first data that is stored in a first area corresponding to a first part of the address, of the volatile memory, and transmit, through a tag data line, a first tag that is stored in the first area.

12. The nonvolatile memory device of claim 11, wherein the first data is transmitted to an external device after a time period elapses from a point in time when the first device read command and the address are received from the external device, and

wherein the nonvolatile memory device further comprises a serial presence detect chip configured to transmit, to the external device, information of the time period.

13. The nonvolatile memory device of claim 11, wherein the second controller is further configured to:

receive the first tag transmitted from the volatile memory through the tag data line;

determine whether a cache hit occurs, based on the first tag that is received and the address; and

transmit, to an external device, a result of the determination.

14. The nonvolatile memory device of claim 13, wherein the first controller is further configured to, in response to the determination that the cache hit does not occur, read second data from a second area corresponding to the address, of the nonvolatile memory.

15. The nonvolatile memory device of claim 14, wherein the second controller is further configured to:

receive, from the external device, a second device read command and the address; and

transmit a first write command and the address to the volatile memory through the first bus, and transmit a third read command and the address to the first controller through the second bus, in response to the second device read command and the address being received.

16. The nonvolatile memory device of claim 15, wherein the first controller is further configured to transmit the second data that is read, through the memory data line in response to the third read command and the address being transmitted.

17. The nonvolatile memory device of claim 16, wherein the volatile memory is further configured to receive the second data transmitted from the first controller through the memory data line, and store the second data that is received in the first area of the volatile memory, in response to the first write command and the address being transmitted.

18. The nonvolatile memory device of claim 16, wherein the first controller is further configured to transmit, through the tag data line, a second tag comprising a second part of the address in synchronization with a point in time when the second data is transmitted through the memory data line.

19. A nonvolatile memory device comprising:

a nonvolatile memory;

a volatile memory being a cache memory of the nonvolatile memory;

a first controller configured to share a memory data line with the volatile memory, and control the nonvolatile memory; and

a second controller configured to;

share a tag data line with the volatile memory and the first controller;

receive a first device read command and an address from an external device; and

transmit a first read command and the address to the volatile memory through a first bus, and transmit a second read command and the address to the first controller through a second bus, in response to the first device read command and the address being received,

wherein the volatile memory is configured to, in response to the first read command and the address being transmitted, transmit, through the memory data line, first data that is stored in a first area corresponding to a part of the address, of the volatile memory, and transmit, through the tag data line, a tag that is stored in the first area, and

wherein the second controller is further configured to;

receive the tag transmitted from the volatile memory through the tag data line;

determine whether a cache hit occurs, based on the tag that is received and the address; and

transmit, to the external device, a result of the determination.