Memory having a static cache and a dynamic cache

• US 10,303,614 B2
• Filed: 08/31/2018
• Issued: 05/28/2019
• Est. Priority Date: 06/10/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hale, Christopher S., Ratnam, Sampath K., Muchherla, Kishore K.
• Primary Examiner(s): Lane, John A
• Application Number:
  US16/118,901
• Publication Number:
  US 20180373639A1
• Time in Patent Office: 270 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Claims

1. An apparatus, comprising:

a memory, wherein the memory includes;

a first portion configured to operate as a static single level cell (SLC) cache;

a second portion configured to;

operate as a dynamic SLC cache when all of the first portion of the memory has data stored therein; and

operate as multilevel cell (MLC) memory when less than all of the first portion of the memory has data stored therein; and

a third portion configured to operate as MLC memory.

2. The apparatus of claim 1, wherein the first portion of the memory is configured to operate as the static SLC cache for an entire lifetime of the memory.

3. The apparatus of claim 1, wherein the third portion of the memory is configured to operate as MLC memory for an entire lifetime of the memory.

4. The apparatus of claim 1, wherein the first portion of the memory, the second portion of the memory, and the third portion of the memory each include a number of physical blocks of memory cells.

5. The apparatus of claim 1, wherein the first portion of the memory is smaller than the second portion of the memory and the third portion of the memory.

6. The apparatus of claim 1, wherein:

the first portion of the memory, the second portion of the memory, and the third portion of the memory each include a first sub-portion, a second sub-portion, and a third sub-portion;

a first logical unit number is associated with the first sub-portion of the first, second, and third portions of the memory;

a second logical unit number is associated with the second sub-portion of the first, second, and third portions of the memory; and

a third logical unit number is associated with the third sub-portion of the first, second, and third portions of the memory.

7. A method of operating memory, comprising:

continuously operating a first portion of a memory as a static single level cell (SLC) cache;

operating a second portion of the memory as a dynamic SLC cache when all of the first portion of the memory has data stored therein;

operating the second portion of the memory as multilevel cell (MLC) memory when less than all of the first portion of the memory has data stored therein; and

continuously operating a third portion of the memory as MLC memory.

8. The method of claim 7, wherein:

the first portion of the memory includes a number of sub-portions; and

the method includes associating a different logical unit number with each respective one of the number of sub-portions of the first portion of the memory.

9. The method of claim 7, wherein:

the second portion of the memory includes a number of sub-portions; and

the method includes associating a different logical unit number with each respective one of the number of sub-portions of the second portion of the memory.

10. The method of claim 7, wherein:

the third portion of the memory includes a number of sub-portions; and

the method includes associating a different logical unit number with each respective one of the number of sub-portions of the third portion of the memory.

11. The method of claim 7, wherein continuously operating the first portion of the memory as the SLC cache includes continuously operating the first portion of the memory as a dedicated cache in SLC mode.

12. The method of claim 7, wherein:

operating the second portion of the memory as the dynamic SLC cache includes operating the second portion of the memory as an overflow cache in SLC mode; and

operating the second portion of the memory as MLC memory includes operating the second portion of the memory as standard MLC memory in MLC storage mode.

13. The method of claim 7, wherein continuously operating the third portion of the memory as MLC memory includes continuously operating the third portion of the memory as standard MLC memory in MLC storage mode.

14. The method of claim 7, wherein the method includes:

continuously operating the first portion of the memory as the SLC cache using a controller of the memory;

operating the second portion of the memory as the dynamic SLC cache and MLC memory using the controller of the memory; and

continuously operating the third portion of the memory as MLC memory using the controller of the memory.

15. An apparatus, comprising:

a memory, wherein the memory includes;

a first number of blocks of memory cells configured to operate as a static single level cell (SLC) cache;

a second number of blocks of memory cells configured to;

operate as a dynamic SLC cache when all of the first number of blocks of memory cells have data stored therein; and

operate as multilevel cell (MLC) memory when less than all of the first number of blocks of memory cells have data stored therein; and

a third number of blocks of memory cells configured to operate as MLC memory.

16. The apparatus of claim 15, wherein the first number of blocks of memory cells comprises 2-3% of the total number of blocks of memory cells of the memory.

17. The apparatus of claim 15, wherein the first number of blocks of memory cells, the second number of blocks of memory cells, and the third number of blocks of memory cells comprise contiguous blocks of memory cells of the memory.

18. The apparatus of claim 15, wherein:

all of the first number of blocks of memory cells have data stored therein when none of the first number of blocks of memory cells are free; and

less than all of the first number of blocks of memory cells have data stored therein when at least one of the first number of blocks of memory cells is free.

19. The apparatus of claim 15, wherein the second number of blocks of memory cells are configured to operate as the dynamic SLC cache until up to a particular point in a lifetime of the memory.

20. The apparatus of claim 15, wherein the third number of blocks of memory cells are configured to not operate as part of the static SLC cache or the dynamic SLC cache.