Systems and methods involving data bus inversion memory circuitry, configuration(s) and/or operation
First Claim
Patent Images
1. A memory device comprising:
- a memory core;
input circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer;
section circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output, wherein the memory device stores and processes the DBI bit on an internal data bus as a regular data bit; and
a data buffering circuit coupled to the memory core, the data buffering circuit including a write buffer comprising a data register positioned between the input circuitry and the DBI logic and storing the data to be written into the memory core on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the data register is retrieved as an output data signal instead of data from the DBI logic when the comparator determines that the address stored in the address register matches the read address, thereby causing the output data signal to bypass the DBI logic.
1 Assignment
0 Petitions
Accused Products
Abstract
Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (OBI) bit associated with a data signal as input directly, without transmission through OBI logic associated with an input buffer, and circuitry that stores the OBI bit into the memory core, reads the OBI bit from the memory core, and provides the OBI bit as output. In further implementations, memory devices herein may store and process the OBI bit on an internal data bus as a regular data bit.
-
Citations
39 Claims
-
1. A memory device comprising:
-
a memory core; input circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer; section circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output, wherein the memory device stores and processes the DBI bit on an internal data bus as a regular data bit; and a data buffering circuit coupled to the memory core, the data buffering circuit including a write buffer comprising a data register positioned between the input circuitry and the DBI logic and storing the data to be written into the memory core on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the data register is retrieved as an output data signal instead of data from the DBI logic when the comparator determines that the address stored in the address register matches the read address, thereby causing the output data signal to bypass the DBI logic. - View Dependent Claims (2, 3, 4)
-
-
5. A memory device comprising:
-
a memory array; local data writing circuitry coupled to the memory array, the local data writing circuitry comprising a local data write driver and a local data bus inversion (DBI) converter logic, wherein the local DBI converter logic includes circuitry that converts DBI formatted data to non-DBI formatted data, and wherein the local data writing circuitry writes the non-DBI formatted data to the memory array; sense circuitry coupled to the memory array and configured to read out the non-DBI formatted data and output sense data; a DBI formatter circuit coupled to an output of the sense circuitry and configured to format the sense data into DBI formatted data and a DBI bit, an output buffer coupled to an output of the DBI formatter circuitry and configured to output the DBI bit and DBI formatted data; and a data buffering circuit including a write buffer comprising a data register coupled to the local DBI converter logic and storing non-converted data to be written into the memory array on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the data register is retrieved as an output data signal instead of data from the memory array when the comparator determines that the address stored in the address register matches the read address, thereby causing the non-converted data to bypass the local DBI converter logic. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12)
-
-
13. A memory device comprising:
-
a memory array; sense circuitry coupled to the memory array, the sense circuitry comprising a section sense amplifier, data bus inversion (DBI) converter logic, and an internal bus for a DBI signal; an input buffer coupled to an input of the sense circuitry and configured to perform DBI formatter logic; wherein the sense circuitry is configured to; process data bits and an associated DBI bit that are received together; perform DBI converter logic; convert the data bits; write the data bits onto bit lines; read the data bits from the memory array; and provide the data bits as output; and a data buffering circuit including a write buffer comprising a data register coupled to the DBI converter logic and storing non-converted data to be written into the memory array on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the data register is retrieved as an output data signal instead of data from the memory array when the comparator determines that the address stored in the address register matches the read address, thereby causing the non-converted data to bypass the DBI converter logic. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
-
-
23. A memory device comprising:
-
a local data writing circuit receiving a plurality of data and a data bus inversion signal corresponding to the plurality of data, wherein the local data writing circuit comprises data bus inversion circuitry to invert the plurality of data based on the data bus inversion signal, and the local data writing circuit outputting the plurality of data to store in a memory core; a sense circuit reading the plurality of data stored in the memory core and outputting the stored plurality of data to another data bus inversion circuit provided at an output of the sense circuit to generate a data bus inversion signal; and a data buffering circuit coupled to the data bus inversion circuitry and including a write buffer comprising a data register storing the data to be written into the memory core on a later cycle, an address register storing addresses corresponding to the stored data signal, and a comparator comparing a read address to the addresses stored in the write buffer, wherein data from the data register is retrieved as an output data signal instead of data from the local data writing circuit when the comparator determines that the address stored in the address register matches the read address, thereby causing the output data signal to bypass the local data writing circuit.
-
-
24. An SRAM or synchronous memory, comprising:
-
a memory array storing non-data bus inversion (non-DBI) formatted data; data input registers and/or latches receiving and storing a data bus inversion (DBI) formatted data and a DBI bit; data output registers and/or latches outputting DBI formatted data; DBI converter circuitry coupled to the data input registers and the memory array; DBI formatter circuitry coupled to the memory array and the data output registers; and a write buffer, comprising; data registers and/or latches coupled to the DBI converter circuitry and storing non-converted data to be written into the memory array on a later cycle, write address registers and/or latches corresponding to the data input registers/latches and storing addresses corresponding to the stored data signal, an address comparator comparing a read address and write addresses stored in the write buffer, wherein the data output registers output the data from the data register instead of data from the memory array when the comparator determines that the address stored in the address register matches a read address, thereby causing the DBI formatted data from the data input registers to bypass the DBI converter circuitry. - View Dependent Claims (25, 26, 27, 28)
-
-
29. An SRAM or synchronous memory system, comprising:
-
a memory array storing data bus inversion (DBI) formatted data and a DBI bit; data input registers/latches receiving and storing the DBI formatted data and the DBI bit; data output registers/latches sending the DBI formatted data to an output; and a write buffer, comprising; data registers and/or latches storing non-converted data to be written into the memory array on a later cycle, write address registers and/or latches corresponding to the data input registers/latches and storing addresses corresponding to the stored data signal, an address comparator comparing a read address and write addresses stored in the write buffer, wherein the data output registers output data from the data register instead of data from the memory array when the comparator determines that the address stored in the address register matches a read address, thereby causing the DBI formatted data from the data input registers to bypass the DBI converter circuitry. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
-
Specification