Secure processor and a program for a secure processor

• US 10,303,901 B2
• Filed: 11/01/2016
• Issued: 05/28/2019
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: Goto, Seiji, Kamada, Jun, Tamiya, Taiji
• Primary Examiner(s): Rahim, Monjur
• Application Number:
  US15/340,061
• Publication Number:
  US 20170046538A1
• Time in Patent Office: 938 Days
• Field of Search: 726 16
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/53 by executing in a restricted environment, e.g. sandbox or secure virtual machine
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/70 Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency

Abstract

The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Claims

1. A processor configured to operate in a first mode in which an access to a secure address space is permitted or in a second mode in which an access to the secure address space is prohibited, the processor comprising:

an execution circuit configured to output a first virtual address; and

a memory access control circuit including a translation look aside buffer which includes a plurality of entries, each of the plurality of entries being configured to include a virtual address and a physical address corresponding to the virtual address, the plurality of entries being configured to include a first subset configured to be referred in the first mode and second subset which is different from the first subset and is configured to be referred in the second mode, the memory access control circuit being configured to output a first physical address corresponding to the first virtual address by referring to the first subset of the translation look aside buffer in the first mode and the second subset of the translation look aside buffer in the second mode,

wherein, by executing a first instruction code stored in the secure address space in the first mode, an second instruction code is checked in the first mode before the second instruction code is executed in the second mode, and

the memory access control circuit prohibits an access to the secure address space in the second mode in accordance with the second subset of the translation look aside buffer.

2. The processor of claim 1, comprising

a first register configured to store mode information which indicates whether the processor is in the first mode or in the second mode.

3. The processor of claim 1,

wherein the first subset of the translation look aside buffer and the second subset of the translation look aside buffer share at least a part of the plurality of entries.

4. The processor of claim 1, comprising

a second register configured to store first context identifier information which indicates whether the first virtual address is associated with the first mode or the second mode,

wherein each of the plurality of entries is configured to include second context identifier information which indicates the virtual address included therein is associated with the first mode or the second mode, and

the memory access control circuit is configured to output the first physical address when the first context identifier information matches the second context identifier information.

5. The processor of claim 4,

wherein each of the plurality of entries is configured to include first flag information which indicates whether the physical address included therein is in the secure address space or not, and

the memory access control circuit is configured to output the first physical address when the first context identifier information and the second context identifier information indicate that the first virtual address is associated with the first mode and the first flag information indicates that the first physical address is in the secure address space.

6. A processor comprising:

an execution circuit configured to output a first virtual address;

a mode register configured to indicate whether the processor is in a first mode in which an access to a secure address space is permitted or in a second mode in which an access to the secure address space is prohibited; and

a memory access control circuit configured to output a first physical address corresponding to the first virtual address by referring to a first subset of a plurality of entries of a transaction look aside buffer in the first mode and a second subset of the plurality of entries of the translation look aside buffer in the second mode, the second subset being different from the first subset,

wherein, by executing a first instruction code stored in the secure address space in the first mode, an second instruction code is checked in the first mode before the second instruction code is executed in the second mode, and

the memory access control unit prohibits an access to the secure address space in the second mode in accordance with the second subset of the translation look aside buffer.

7. The processor of claim 6,

wherein the first subset of the translation look aside buffer and the second subset of the translation look aside buffer share at least a part of the plurality of entries.