Systems and methods of using z-layer context in logic and hot spot inspection for sensitivity improvement and nuisance suppression

• US 10,304,177 B2
• Filed: 05/21/2017
• Issued: 05/28/2019
• Est. Priority Date: 06/29/2016
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Perali, Pavan Kumar, Lee, Hucheng
• Primary Examiner(s): Wu, Jingge
• Application Number:
  US15/600,784
• Publication Number:
  US 20180005367A1
• Time in Patent Office: 737 Days
• CPC Class Codes: G06T 2207/10061 from scanning electron microscope
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0006 using a design-rule based approach
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: G06T 7/70 Determining position or orientation of objects or cameras camera calibration G06T7/80

Abstract

Systems and methods for removing nuisance data from a defect scan of a wafer are disclosed. A processor receives a design file corresponding to a wafer having one or more z-layers. The processor receives critical areas of the wafer and instructs a subsystem to capture corresponding images of the wafer. Defect locations are received and the design file is aligned with the defect locations. Nuisance data is identified using the potential defect location and the one or more z-layers of the aligned design file. The processor then removes the identified nuisance data from the one or more potential defect locations.

Claims

1. A method for removing nuisance data comprising:

receiving, at a processor, a design file corresponding to a wafer, the design file having one or more z-layers;

receiving, at the processor, one or more critical areas of the wafer;

instructing an image data acquisition subsystem to capture one or more images corresponding to the one or more critical areas of the wafer;

receiving, at the processor, one or more potential defect locations in the one or more images corresponding to the one or more critical areas of the wafer;

aligning, using the processor, the design file with the one or more potential defect locations corresponding to the one or more critical areas of the wafer;

creating, using the processor, a synthetic image based on the design file and the one or more images corresponding to the one or more critical areas of the wafer;

identifying, using the processor, nuisance data in the one or more potential defect locations based on each potential defect location, the one or more z-layers of the aligned design file, and the synthetic image; and

removing, using the processor, the identified nuisance data from the one or more potential defect locations.

2. The method of claim 1, further comprising:

analyzing the design file, using the processor, to determine the one or more critical areas of the wafer based on pre-determined design rules.

3. The method of claim 1, wherein the nuisance data is identified based on whether the location of each potential defect location is proximal to pattern data in each z-layer of the aligned design file.

4. The method of claim 1, wherein the critical areas of the wafer are based on predetermined patterns in the design file.

5. The method of claim 1, wherein the critical areas of the wafer are based on previously identified wafer defects.

6. The method of claim 1, wherein the one or more critical areas comprise data from a run-time context map.

7. The method of claim 1, further comprising:

segmenting, using the processor, the one or more critical areas of the wafer based on the one or more z-layers in the design file.

8. The method of claim 1, wherein the nuisance data is identified based on subpixel defect location, overlap percentage, horizontal distance, or vertical distance to the one or more z-layers in the aligned design file.

9. The method of claim 1, wherein the processor is a single core of a multi-core computer.

10. A system for removing nuisance data comprising:

an image data acquisition subsystem;

a design file database comprising a plurality of design files associated with one or more wafers, each design file having one or more z-layers; and

a multi-core computer in electronic communication with the image data acquisition subsystem, the multi-core computer having a plurality of processors, each processor configured to;

receive a design file from the design file database corresponding to a wafer, the design file having one or more z-layers;

receive one or more images corresponding to one or more critical areas of the wafer;

receive one or more potential defect locations in the one or more images corresponding to the one or more critical areas of the wafer;

align the design file with the one or more potential defect locations corresponding to the one or more critical areas of the wafer;

create a synthetic image based on the design file and the one or more images corresponding to the one or more critical areas of the wafer;

identify nuisance data in the one or more potential defect locations based on each potential defect location, the one or more z-layers of the aligned design file, and the synthetic image; and

remove the identified nuisance data from the one or more potential defect locations.

11. The system of claim 10, wherein each processor is further configured to:

analyze the design file to determine the one or more critical areas of the wafer based on pre-determined design rules.

12. The system of claim 10, wherein the nuisance data is identified based on whether the location of each potential defect location is proximal to pattern data in each z-layer of the aligned design file.

13. The system of claim 10, wherein the critical areas of the wafer are based on predetermined patterns in the design file.

14. The system of claim 10, wherein the critical areas of the wafer are based on previously identified wafer defects.

15. The system of claim 10, wherein the one or more critical areas comprise data from a run-time context map.

16. The system of claim 10, wherein each processor is further configured to:

segment the one or more critical areas of the wafer based on the one or more z-layers in the design file.

17. The system of claim 10, wherein the nuisance data is identified based on subpixel defect location, overlap percentage, horizontal distance, or vertical distance to the one or more z-layers in the aligned design file.

18. A non-transitory computer readable medium storing a program configured to instruct a processor to:

receive a design file corresponding to a wafer, the design file having one or more z-layers;

receive one or more critical areas of the wafer;

instruct an image data acquisition subsystem to capture one or more images corresponding to the one or more critical areas of the wafer;

receive one or more potential defect locations in the one or more images corresponding to the one or more critical areas of the wafer;

align the design file with the one or more potential defect locations corresponding to the one or more critical areas of the wafer;

create a synthetic image based on the design file and the one or more images corresponding to the one or more critical areas of the wafer;

identify nuisance data in the one or more potential defect locations based on each potential defect location, the one or more z-layers of the aligned design file, and the synthetic image; and

remove the identified nuisance data from the one or more potential defect locations.