Display driving circuit and liquid crystal display panel

• US 10,304,401 B2
• Filed: 03/15/2017
• Issued: 05/28/2019
• Est. Priority Date: 02/07/2017
• Status: Active Grant

• Current Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Zuo, Qingcheng, Li, Man, Yuan, Xiaoling
• Primary Examiner(s): McLoone, Peter D
• Application Number:
  US15/516,898
• Publication Number:
  US 20190096344A1
• Time in Patent Office: 804 Days
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/025 Reduction of instantaneous peaks of current
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

The present invention provides a display driving circuit and a liquid crystal display panel with adding a first AND gate (AND1), a second AND gate (AND2) and a third AND gate (AND3). Two input ends of each of the three gates receives a branch control signal and a conditioning signal (BURR), and the conditioning signal (BURR) first performs several high and low voltage level conversions and then maintains the high voltage level, respectively in the high voltage level durations of the respective branch control signals to make the signal outputted by the output end of the first AND gate, the signal outputted by the output end of the second AND gate and the signal outputted by the output end of the third AND gate first perform several high and low voltage level conversions and then maintain the high voltage level.

Claims

1. A display driving circuit, comprising a plurality of pixel units arranged in array, scan lines set corresponding to each row of pixel units, data lines set corresponding to each column of pixel units, multiplex modules set corresponding to each column of pixel units, and a first AND gate, a second AND gate and a third AND gate;

two input ends of the first AND gate respectively receiving a first branch control signal and a conditioning signal, and two input ends of the second AND gate respectively receiving a second branch control signal and a conditioning signal, and two input ends of the third AND gate respectively receiving a third branch control signal and a conditioning signal;

each pixel unit comprising a red sub pixel, a green sub pixel and a blue sub pixel which are aligned from left to right in order, and a first switch TFT electrically coupled to the red sub pixel, a second switch TFT electrically coupled to the green sub pixel, a third switch TFT electrically coupled to the blue sub pixel;

each multiplex module comprising a first control TFT, a second control TFT and a third control TFT respectively set corresponding to a red sub pixel column, a green sub pixel column and a blue sub pixel column;

n, m are set to be positive integers, and for the pixel unit of a nth row, a mth column;

all of a gate of the first switch TFT, a gate of the second switch TFT and a gate of the third switch TFT being electrically coupled to a nth scan line set corresponding to a nth row of pixel units, and a source of the first switch TFT, a source of the second switch TFT and a source of the third switch TFT being electrically coupled to a drain of the first control TFT, a drain of the second control TFT and a drain of the third control TFT in a mth multiplex module set corresponding to a mth column of pixel units, respectively, and a drain of the first switch TFT, a drain of the second switch TFT and a drain of the third switch TFT being electrically coupled to the red sub pixel, the green sub pixel and the blue sub pixel, respectively;

for the mth multiplex module;

a gate of the first control TFT, a gate of the second control TFT and a gate of the third control TFT being electrically coupled to an output end of the first AND gate, an output end of the second AND gate and an output end of the third AND gate, respectively, and all of a source of the first control TFT, a source of the second control TFT and a source of the third control TFT being electrically coupled to a mth data line set corresponding to the mth column of pixel units.

2. The display driving circuit according to claim 1, wherein a high voltage level duration of the scan signal in the nth scan line is larger than a sum of a high voltage level duration of the first branch control signal, a high voltage level duration of the second branch control signal and a high voltage level duration of the third branch control signal;

the conditioning signal first performs several high and low voltage level conversions and then maintains the high voltage level, respectively in the high voltage level duration of the first branch control signal, the high voltage level duration of the second branch control signal and the high voltage level duration of the third branch control signal, and correspondingly makes a signal outputted by the output end of the first AND gate, a signal outputted by the output end of the second AND gate and a signal outputted by the output end of the third AND gate first perform several high and low voltage level conversions and then maintain the high voltage level.

3. The display driving circuit according to claim 2, wherein in a process that the conditioning signal performs several high and low voltage level conversions, both a high voltage level duration and a low voltage level duration are default durations.

4. The display driving circuit according to claim 2, wherein the first branch control signal, the second branch control signal and the third branch control signal are generated in time sequence, and a rising edge of the second branch control signal is later than a falling edge of the first branch control signal, and a rising edge of the third branch control signal is later than a falling edge of the second branch control signal.

5. The display driving circuit according to claim 1, wherein all of the first switch TFT, the second switch TFT, the third switch TFT, the first control TFT, the second control TFT and the third control TFT are low temperature poly-silicon TFTs, oxide semiconductor TFTs or amorphous silicon TFTs.

6. A liquid crystal display panel, comprising a display driving circuit, and the display driving circuit comprising a plurality of pixel units arranged in array, scan lines set corresponding to each row of pixel units, data lines set corresponding to each column of pixel units, multiplex modules set corresponding to each column of pixel units, and a first AND gate, a second AND gate and a third AND gate;

two input ends of the first AND gate respectively receiving a first branch control signal and a conditioning signal, and two input ends of the second AND gate respectively receiving a second branch control signal and a conditioning signal, and two input ends of the third AND gate respectively receiving a third branch control signal and a conditioning signal;

each pixel unit comprising a red sub pixel, a green sub pixel and a blue sub pixel which are aligned from left to right in order, and a first switch TFT electrically coupled to the red sub pixel, a second switch TFT electrically coupled to the green sub pixel, a third switch TFT electrically coupled to the blue sub pixel;

each multiplex module comprising a first control TFT, a second control TFT and a third control TFT respectively set corresponding to a red sub pixel column, a green sub pixel column and a blue sub pixel column;

n, m are set to be positive integers, and for the pixel unit of a nth row, a mth column;

all of a gate of the first switch TFT, a gate of the second switch TFT and a gate of the third switch TFT being electrically coupled to a nth scan line set corresponding to a nth row of pixel units, and a source of the first switch TFT, a source of the second switch TFT and a source of the third switch TFT being electrically coupled to a drain of the first control TFT, a drain of the second control TFT and a drain of the third control TFT in a mth multiplex module set corresponding to a mth column of pixel units, respectively, and a drain of the first switch TFT, a drain of the second switch TFT and a drain of the third switch TFT being electrically coupled to the red sub pixel, the green sub pixel and the blue sub pixel, respectively;

for the mth multiplex module;

a gate of the first control TFT, a gate of the second control TFT and a gate of the third control TFT being electrically coupled to an output end of the first AND gate, an output end of the second AND gate and an output end of the third AND gate, respectively, and all of a source of the first control TFT, a source of the second control TFT and a source of the third control TFT being electrically coupled to a mth data line set corresponding to the mth column of pixel units.

7. The liquid crystal display panel according to claim 6, wherein a high voltage level duration of the scan signal in the nth scan line is larger than a sum of a high voltage level duration of the first branch control signal, a high voltage level duration of the second branch control signal and a high voltage level duration of the third branch control signal;

the conditioning signal first performs several high and low voltage level conversions and then maintains the high voltage level, respectively in the high voltage level duration of the first branch control signal, the high voltage level duration of the second branch control signal and the high voltage level duration of the third branch control signal, and correspondingly makes a signal outputted by the output end of the first AND gate, a signal outputted by the output end of the second AND gate and a signal outputted by the output end of the third AND gate first perform several high and low voltage level conversions and then maintain the high voltage level.

8. The liquid crystal display panel according to claim 7, wherein in a process that the conditioning signal performs several high and low voltage level conversions, both a high voltage level duration and a low voltage level duration are default durations.

9. The liquid crystal display panel according to claim 7, wherein the first branch control signal, the second branch control signal and the third branch control signal are generated in time sequence, and a rising edge of the second branch control signal is later than a falling edge of the first branch control signal, and a rising edge of the third branch control signal is later than a falling edge of the second branch control signal.

10. The liquid crystal display panel according to claim 6, wherein all of the first switch TFT, the second switch TFT, the third switch TFT, the first control TFT, the second control TFT and the third control TFT are low temperature poly-silicon TFTs, oxide semiconductor TFTs or amorphous silicon TFTs.

11. A liquid crystal display panel, comprising a display driving circuit, and the display driving circuit comprising a plurality of pixel units arranged in array, scan lines set corresponding to each row of pixel units, data lines set corresponding to each column of pixel units, multiplex modules set corresponding to each column of pixel units, and a first AND gate, a second AND gate and a third AND gate;

two input ends of the first AND gate respectively receiving a first branch control signal and a conditioning signal, and two input ends of the second AND gate respectively receiving a second branch control signal and a conditioning signal, and two input ends of the third AND gate respectively receiving a third branch control signal and a conditioning signal;

each pixel unit comprising a red sub pixel, a green sub pixel and a blue sub pixel which are aligned from left to right in order, and a first switch TFT electrically coupled to the red sub pixel, a second switch TFT electrically coupled to the green sub pixel, a third switch TFT electrically coupled to the blue sub pixel;

each multiplex module comprising a first control TFT, a second control TFT and a third control TFT respectively set corresponding to a red sub pixel column, a green sub pixel column and a blue sub pixel column;

n, m are set to be positive integers, and for the pixel unit of a nth row, a mth column;

all of a gate of the first switch TFT, a gate of the second switch TFT and a gate of the third switch TFT being electrically coupled to a nth scan line set corresponding to a nth row of pixel units, and a source of the first switch TFT, a source of the second switch TFT and a source of the third switch TFT being electrically coupled to a drain of the first control TFT, a drain of the second control TFT and a drain of the third control TFT in a mth multiplex module set corresponding to a mth column of pixel units, respectively, and a drain of the first switch TFT, a drain of the second switch TFT and a drain of the third switch TFT being electrically coupled to the red sub pixel, the green sub pixel and the blue sub pixel, respectively;

for the mth multiplex module;

a gate of the first control TFT, a gate of the second control TFT and a gate of the third control TFT being electrically coupled to an output end of the first AND gate, an output end of the second AND gate and an output end of the third AND gate, respectively, and all of a source of the first control TFT, a source of the second control TFT and a source of the third control TFT being electrically coupled to a mth data line set corresponding to the mth column of pixel units;

wherein a high voltage level duration of the scan signal in the nth scan line is larger than a sum of a high voltage level duration of the first branch control signal, a high voltage level duration of the second branch control signal and a high voltage level duration of the third branch control signal;

the conditioning signal first performs several high and low voltage level conversions and then maintains the high voltage level, respectively in the high voltage level duration of the first branch control signal, the high voltage level duration of the second branch control signal and the high voltage level duration of the third branch control signal, and correspondingly makes a signal outputted by the output end of the first AND gate, a signal outputted by the output end of the second AND gate and a signal outputted by the output end of the third AND gate first perform several high and low voltage level conversions and then maintain the high voltage level;

wherein all of the first switch TFT, the second switch TFT, the third switch TFT, the first control TFT, the second control TFT and the third control TFT are low temperature poly-silicon TFTs, oxide semiconductor TFTs or amorphous silicon TFTs.

12. The liquid crystal display panel according to claim 11, wherein in a process that the conditioning signal performs several high and low voltage level conversions, both a high voltage level duration and a low voltage level duration are default durations.

13. The liquid crystal display panel according to claim 11, wherein the first branch control signal, the second branch control signal and the third branch control signal are generated in time sequence, and a rising edge of the second branch control signal is later than a falling edge of the first branch control signal, and a rising edge of the third branch control signal is later than a falling edge of the second branch control signal.