×

Compact three-dimensional memory with semi-conductive address line portion

  • US 10,304,495 B2
  • Filed: 04/13/2017
  • Issued: 05/28/2019
  • Est. Priority Date: 04/14/2014
  • Status: Active Grant
First Claim
Patent Images

1. A compact three-dimensional memory (3D-MC), comprising:

  • a semiconductor substrate with transistors thereon;

    a memory level stacked above said semiconductor substrate, said memory level comprising at least a memory array and at least an above-substrate decoding stage thereof; and

    at least a contact via coupling said memory level with said semiconductor substrate;

    wherein said memory array comprises;

    a first address-line extending from said memory array to said above-substrate decoding stage;

    a second address-line intersecting said first address-line;

    a memory device located at the intersection of said first and second address-lines, said memory device comprising a diode or a diode-like device;

    said above-substrate decoding stage comprises;

    a control line intersecting said first address-line;

    a decoding device located at the intersection of said first address-line and said control line, said decoding device being positioned between said memory device and said contact via, said decoding device comprising a transistor or a transistor-like device;

    wherein said decoding device has a conduction mode and a blocking mode;

    in said conduction mode, said decoding device is switched on to allow current conduction in said first address-line;

    in said blocking mode, said decoding device is switched off to block current conduction in said first address-line;

    wherein said memory device and said decoding device are located on a same memory level.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×