Compact three-dimensional memory with semi-conductive address line portion
First Claim
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1. A compact three-dimensional memory (3D-MC), comprising:
- a semiconductor substrate with transistors thereon;
a memory level stacked above said semiconductor substrate, said memory level comprising at least a memory array and at least an above-substrate decoding stage thereof; and
at least a contact via coupling said memory level with said semiconductor substrate;
wherein said memory array comprises;
a first address-line extending from said memory array to said above-substrate decoding stage;
a second address-line intersecting said first address-line;
a memory device located at the intersection of said first and second address-lines, said memory device comprising a diode or a diode-like device;
said above-substrate decoding stage comprises;
a control line intersecting said first address-line;
a decoding device located at the intersection of said first address-line and said control line, said decoding device being positioned between said memory device and said contact via, said decoding device comprising a transistor or a transistor-like device;
wherein said decoding device has a conduction mode and a blocking mode;
in said conduction mode, said decoding device is switched on to allow current conduction in said first address-line;
in said blocking mode, said decoding device is switched off to block current conduction in said first address-line;
wherein said memory device and said decoding device are located on a same memory level.
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Abstract
In a compact three-dimensional memory (3D-MC), a memory array and an above-substrate decoding stage thereof are formed on a same memory level. For the memory devices in the memory array, the overlap portion and the non-overlap portions of the x-line are both highly-conductive; for the decoding device in the above-substrate decoding stage, while the non-overlap portions are still highly-conductive, the overlap portion is semi-conductive.
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Citations
20 Claims
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1. A compact three-dimensional memory (3D-MC), comprising:
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a semiconductor substrate with transistors thereon; a memory level stacked above said semiconductor substrate, said memory level comprising at least a memory array and at least an above-substrate decoding stage thereof; and at least a contact via coupling said memory level with said semiconductor substrate; wherein said memory array comprises; a first address-line extending from said memory array to said above-substrate decoding stage; a second address-line intersecting said first address-line; a memory device located at the intersection of said first and second address-lines, said memory device comprising a diode or a diode-like device; said above-substrate decoding stage comprises; a control line intersecting said first address-line; a decoding device located at the intersection of said first address-line and said control line, said decoding device being positioned between said memory device and said contact via, said decoding device comprising a transistor or a transistor-like device; wherein said decoding device has a conduction mode and a blocking mode;
in said conduction mode, said decoding device is switched on to allow current conduction in said first address-line;
in said blocking mode, said decoding device is switched off to block current conduction in said first address-line;wherein said memory device and said decoding device are located on a same memory level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A compact three-dimensional memory (3D-MC), comprising:
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a semiconductor substrate with transistors thereon; a memory level stacked above said semiconductor substrate, said memory level comprising at least a memory array and at least an above-substrate decoding stage thereof; and at least a contact via coupling said memory level with said semiconductor substrate; wherein said memory array comprises; a first address-line extending from said memory array to said above-substrate decoding stage; a second address-line intersecting said first address-line; a memory device located at the intersection of said first and second address-lines, wherein the overlap portion and the non-overlap portions of said first address-line with said second address-line have the same electrical characteristics; said above-substrate decoding stage comprises; a control line intersecting said first address-line; a decoding device located at the intersection of said first address-line and said control line, said decoding device being positioned between said memory device and said contact via, wherein the overlap portion and the non-overlap portions of said first address-line with said control line have different electrical characteristics; wherein said decoding device has a conduction mode and a blocking mode;
in said conduction mode, said decoding device is switched on to allow current conduction in said first address-line;
in said blocking mode, said decoding device is switched off to block current conduction in said first address-line;wherein said memory device and said decoding device are located on a same memory level. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification