Magnetoresistive element and memory circuit including a free layer

• US 10,304,508 B2
• Filed: 05/31/2016
• Issued: 05/28/2019
• Est. Priority Date: 06/03/2015
• Status: Active Grant

• Current Assignee: Japan Science & Technology Trading Co. Limited
• Original Assignee: Japan Science & Technology Trading Co. Limited
• Inventors: Sugahara, Satoshi, Takamura, Yota, Nakagawa, Shigeki
• Primary Examiner(s): Lam, David
• Application Number:
  US15/578,377
• Publication Number:
  US 20180158496A1
• Time in Patent Office: 1,092 Days
• CPC Class Codes: G11C 11/14 using thin-film elements
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/82 controllable by variation of the magnetic field applied to the device
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 30/20 with electrical input and mechanical output, e.g. functioning as actuators or vibrators
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A magnetoresistive element includes: a free layer that includes a magnetostrictive layer containing a magnetostrictive material; a pin layer that includes a first ferromagnetic layer; a thin film that is located between the pin layer and the free layer; a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer from a direction intersecting with a stacking direction of the free layer and the pin layer and applies a pressure to the magnetostrictive layer; and an electrode that is capable of applying a voltage different from a voltage applied to the free layer and a voltage applied to the pin layer and applies a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer.

Claims

1. A magnetoresistive element comprising:

a free layer that includes a magnetostrictive layer containing a magnetostrictive material;

a pin layer that includes a first ferromagnetic layer;

a thin film that is located between the pin layer and the free layer;

a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer from a direction intersecting with a stacking direction of the free layer and the pin layer and applies a pressure to the magnetostrictive layer; and

an electrode that is capable of applying a voltage different from a voltage applied to the free layer and a voltage applied to the pin layer and applies a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer in an identical direction when a parallel state is rewritten to an antiparallel state and when the antiparallel state is rewritten to the parallel state, a magnetization direction of the free layer being parallel to that of the pin layer in the parallel state, the magnetization direction of the free layer being opposite to that of the pin layer in the antiparallel state.

2. The magnetoresistive element according to claim 1, wherein

the electrode includes a first electrode and a second electrode located at both sides in the stacking direction with respect to the piezoelectric substance, and

the piezoelectric substance is dielectrically polarized in the stacking direction.

3. The magnetoresistive element according to claim 2, wherein

when a polarity of a voltage applied to the pin layer with respect to the free layer reverses, a polarity of a voltage applied to the second electrode with respect to the first electrode does not change.

4. The magnetoresistive element according to claim 1, wherein

the free layer includes a second ferromagnetic layer magnetically coupled to the magnetostrictive layer so that a magnetization direction of the second ferromagnetic layer is reversed when a magnetization of the magnetostrictive layer is reversed.

5. The magnetoresistive element according to claim 1, wherein

the magnetostrictive layer changes a direction of a magnetization easy axis thereof by application of pressure and reverses a magnetization direction of the free layer.

6. The magnetoresistive element according to claim 5, wherein

the magnetization direction of the free layer is reversed by spin-transfer-torque current-induced magnetization switching when the direction of the magnetization easy axis of the magnetostrictive layer changes.

7. The magnetoresistive element according to claim 1, wherein

the thin film includes a tunnel barrier insulating layer or a non-magnetic metal layer.

8. A memory circuit comprising:

the magnetoresistive element according to claim 7;

a bit line to which one of the free layer and the pin layer is coupled;

a switch coupled to another of the free layer and the pin layer;

a source line coupled to the another of the free layer and the pin layer through the switch;

a word line to which a control terminal controlling the switch is coupled; and

a control line to which the electrode is coupled.

9. The magnetoresistive element according to claim 1, wherein

the thin film includes a piezoresistor, and

the piezoelectric substance applies a pressure to the piezoresistor.

10. A memory circuit comprising:

the magnetoresistive element according to claim 9;

a bit line to which one of the free layer and the pin layer is coupled;

a source line coupled to another of the free layer and the pin layer; and

a word line coupled to the electrode.

11. The magnetoresistive element according to claim 1, wherein

the piezoelectric substance is located outside the at least the part of the magnetostrictive layer in a plurality of directions, and the plurality of directions intersects with the stacking direction and include two intersecting direction.

12. The magnetoresistive element according to claim 11, wherein

the electrode is located outside at least a part of the piezoelectric substance in the plurality of directions, and

the piezoelectric substance is dielectrically polarized in a direction from the magnetostrictive layer to the electrode or a direction from the electrode to the magnetostrictive layer.

13. The magnetoresistive element according to claim 12, wherein

when a polarity of a voltage applied to the pin layer with respect to the free layer reverses, a polarity of a voltage applied to the electrode with respect to the free layer does not change.

14. A memory circuit comprising:

a magnetoresistive element including;

a free layer that includes a magnetostrictive layer containing a magnetostrictive material;

a pin layer that includes a first ferromagnetic layer;

a thin film that is located between the pin layer and the free layer;

a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer from a direction intersecting with a stacking direction of the free layer and the pin layer, and applies a pressure to the magnetostrictive layer; and

an electrode that is capable of applying a voltage different from a voltage applied to the free layer and a voltage applied to the pin layer, and applies a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer in an identical direction when a parallel state is rewritten to an antiparallel state and when the antiparallel state is rewritten to the parallel state, a magnetization direction of the free layer being parallel to that of the pin layer in the parallel state, the magnetization direction of the free layer being opposite to that of the pin layer in the antiparallel state; and

a transistor including;

a source and a drain, one of the source and the drain being coupled to one of the free layer and the pin layer;

a channel that is located between the source and the drain and through which a carrier conducts from the source to the drain; and

a gate that surrounds at least a part of the channel from the intersecting direction, wherein

the source, the channel, and the drain are stacked in the stacking direction.

15. The memory circuit according to claim 14, wherein

the channel is a piezoresistor, and

the gate includes a piezoelectric substance that applies a pressure to the channel from a direction intersecting with a direction in which the carrier conducts.