Method for low power operation and test using DRAM device

• US 10,304,522 B2
• Filed: 01/31/2017
• Issued: 05/28/2019
• Est. Priority Date: 01/31/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Erickson, Karl R., Paone, Phil C., Paulsen, David P., Sheets, II, John E., Uhlmann, Gregory J.
• Primary Examiner(s): Siddique, Mushfique
• Application Number:
  US15/420,679
• Publication Number:
  US 20180218766A1
• Time in Patent Office: 847 Days
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Big data analysis using low power circuit design including storing a plurality of data bits in a plurality of cells on a bitline of a dynamic random access memory (DRAM), wherein each data bit corresponds to a test result, and wherein each of the plurality of cells on the bitline is associated with a different wordline; precharging the bitline to a midpoint voltage between a low voltage corresponding to a low data bit and a high voltage corresponding to a high data bit; activating, at the same time, each wordline associated with each of the plurality of cells on the bitline, wherein activating each wordline causes a voltage to be applied to the bitline from each of the plurality of cells; and measuring a resulting voltage on the bitline to obtain a value corresponding to a percentage of the test results that indicate a passing test result.

Claims

1. A method comprising:

storing a plurality of data bits in a plurality of cells on a bitline of a dynamic random access memory (DRAM), wherein each data bit corresponds to a test result, wherein each test result consists of one of a passing test result or a failing test result, and wherein each of the plurality of cells on the bitline is associated with a different wordline;

precharging the bitline to a midpoint voltage between a low voltage corresponding to a low data bit and a high voltage corresponding to a high data bit;

activating, at the same time, each wordline associated with each of the plurality of cells on the bitline, wherein activating each wordline causes a voltage to be applied to the bitline from each of the plurality of cells wherein activating, at the same time, each wordline associated with each of the plurality of cells on the bitline comprises;

activating a special correlation function comprising logic configured to activate all connected wordlines simultaneously and cause each memory cell on a bitline to apply a voltage to the bitline, the special correlation function operatively coupled to each wordline associated with each of the plurality of cells on the bitline; and

measuring a resulting voltage between the low voltage and the high voltage on the bitline to obtain a value corresponding to a percentage of the test results that indicate a passing test result;

wherein each data bit in the plurality of cells on the bitline corresponds to a test result from a same test performed under different conditions;

wherein measuring the resulting voltage on the bitline to obtain the value corresponding to the percentage of the test results that indicate a passing test result comprises;

applying the resulting voltage to a correlation unit comprising an analog-to-digital converter; and

activating, based on the resulting voltage, a correlation factor indicating the percentage of passing test results.

2. The method of claim 1, wherein the correlation unit comprises a plurality of correlation factors, and wherein activating, based on the resulting voltage, the correlation factor indicating the percentage of passing test results comprises activating at least two correlation factors of the plurality of correlation factors indicating the percentage of passing test results.

3. The method of claim 1, wherein activating the special correlation function transmits a high signal to an OR gate attached to each wordline associated with each of the plurality of cells on the bitline.

4. The method of claim 1, wherein each of the plurality of cells on the bitline is refreshed prior to activating each wordline associated with each of the plurality of cells on the bitline.

5. The method of claim 1, wherein each cell on a wordline stores test results from a different test performed under a same condition.

6. An apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, wherein computer program instructions are stored within the computer memory and the computer program instructions, when executed by the computer processor, cause the apparatus to carry out the steps of:

storing a plurality of data bits in a plurality of cells on a bitline of a dynamic random access memory (DRAM), wherein each data bit corresponds to a test result, wherein each test result consists of one of a passing test result or a failing test result, and wherein each of the plurality of cells on the bitline is associated with a different wordline;

precharging the bitline to a midpoint voltage between a low voltage corresponding to a low data bit and a high voltage corresponding to a high data bit;

activating, at the same time, each wordline associated with each of the plurality of cells on the bitline, wherein activating each wordline causes a voltage to be applied to the bitline from each of the plurality of cells, wherein activating, at the same time, each wordline associated with each of the plurality of cells on the bitline comprises;

activating a special correlation function comprising logic configured to activate all connected wordlines simultaneously and cause each memory cell on a bitline to apply a voltage to the bitline, the special correlation function operatively coupled to each wordline associated with each of the plurality of cells on the bitline; and

measuring a resulting voltage between the low voltage and the high voltage on the bitline to obtain a value corresponding to a percentage of the test results that indicate a passing test result;

wherein each data bit in the plurality of cells on the bitline corresponds to a test result from a same test performed under different conditions;

wherein measuring the resulting voltage on the bitline to obtain the value corresponding to the percentage of the test results that indicate a passing test result comprises;

applying the resulting voltage to a correlation unit comprising an analog-to-digital converter; and

activating, based on the resulting voltage, a correlation factor indicating the percentage of passing test results.

7. The apparatus of claim 6, wherein the correlation unit comprises a plurality of correlation factors, and wherein activating, based on the resulting voltage, the correlation factor indicating the percentage of passing test results comprises activating at least two correlation factors of the plurality of correlation factors indicating the percentage of passing test results.

8. The apparatus of claim 6, wherein activating the special correlation function transmits a high signal to an OR gate attached to each wordline associated with each of the plurality of cells on the bitline.

9. The apparatus of claim 6, wherein each of the plurality of cells on the bitline is refreshed prior to activating each wordline associated with each of the plurality of cells on the bitline.

10. The apparatus of claim 6, wherein each cell on a wordline stores test results from a different test performed under a same condition.

11. A non-transitory computer readable medium comprising computer program instructions that, when executed, cause a computer to carry out the steps of:

storing a plurality of data bits in a plurality of cells on a bitline of a dynamic random access memory (DRAM), wherein each data bit corresponds to a test result, wherein each test result consists of one of a passing test result or a failing test result, and wherein each of the plurality of cells on the bitline is associated with a different wordline;

precharging the bitline to a midpoint voltage between a low voltage corresponding to a low data bit and a high voltage corresponding to a high data bit;

activating, at the same time, each wordline associated with each of the plurality of cells on the bitline, wherein activating each wordline causes a voltage to be applied to the bitline from each of the plurality of cells, wherein activating, at the same time, each wordline associated with each of the plurality of cells on the bitline comprises;

activating a special correlation function comprising logic configured to activate all connected wordlines simultaneously and cause each memory cell on a bitline to apply a voltage to the bitline, the special correlation function operatively coupled to each wordline associated with each of the plurality of cells on the bitline; and

measuring a resulting voltage between the low voltage and the high voltage on the bitline to obtain a value corresponding to a percentage of the test results that indicate a passing test result;

wherein each data bit in the plurality of cells on the bitline corresponds to a test result from a same test performed under different conditions;

wherein measuring the resulting voltage on the bitline to obtain the value corresponding to the percentage of the test results that indicate a passing test result comprises;

applying the resulting voltage to a correlation unit comprising an analog-to-digital converter; and

activating, based on the resulting voltage, a correlation factor indicating the percentage of passing test results.

12. The non-transitory computer readable medium of claim 11, wherein the correlation unit comprises a plurality of correlation factors, and wherein activating, based on the resulting voltage, the correlation factor indicating the percentage of passing test results comprises activating at least two correlation factors of the plurality of correlation factors indicating the percentage of passing test results.

13. The non-transitory computer readable medium of claim 11, wherein activating the special correlation function transmits a high signal to an OR gate attached to each wordline associated with each of the plurality of cells on the bitline.

14. The non-transitory computer readable medium of claim 11, wherein each of the plurality of cells on the bitline is refreshed prior to activating each wordline associated with each of the plurality of cells on the bitline.

15. The non-transitory computer readable medium of claim 11, wherein each cell on a wordline stores test results from a different test performed under a same condition.