Semiconductor structure and memory device including the structure

• US 10,304,524 B2
• Filed: 06/22/2017
• Issued: 05/28/2019
• Est. Priority Date: 03/21/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Tailliet, Francois, Battista, Marc
• Primary Examiner(s): Pham, Long
• Application Number:
  US15/630,614
• Publication Number:
  US 20170294225A1
• Time in Patent Office: 705 Days
• Field of Search: None
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

Claims

1. A semiconductor structure, comprising:

a semiconductor body;

a first source/drain region disposed in the semiconductor body;

a second source/drain region disposed in the semiconductor body and spaced apart from the first source/drain region by a channel region;

a gate electrode overlying the channel region;

a first gate dielectric located between the gate electrode and the channel region;

a capacitor having a first capacitor electrode formed by the gate electrode, a second capacitor electrode located above the gate electrode and a second gate dielectric located between the gate electrode and the second capacitor electrode;

a first contact region in electrical contact with the gate electrode; and

a second contact region in electrical contact with the second capacitor electrode, the first contact region and the second contact region being electrically isolated from one another, wherein the first contact region comprises a first metal track portion and a first contact via, wherein the first contact via physically contacts the first metal track portion and the gate electrode, wherein a width of the first contact via is uniform along a length of the first contact via, wherein the width of the first contact via is less than a width of the first metal track portion, and wherein no portion of the second gate dielectric is disposed between the first metal track portion and the gate electrode and no portion of the second gate dielectric physically contacts the first contact via.

2. The semiconductor structure of claim 1, wherein the second gate dielectric is located above the first gate dielectric.

3. The semiconductor structure of claim 1, wherein a thickness of the first gate dielectric is between 20 angstroms and 250 angstroms.

4. The semiconductor structure of claim 1, wherein a thickness of the second gate dielectric is between 100 angstroms and 200 angstroms.

5. The semiconductor structure of claim 1, wherein the second gate dielectric comprises a silicon nitride layer sandwiched between two silicon dioxide layers.

6. The semiconductor structure of claim 1, wherein the second capacitor electrode is coupled to an output of an inverter.

7. The semiconductor structure of claim 1, wherein the second capacitor electrode is coupled to an output of a reference voltage node.

8. A semiconductor structure, comprising:

a metal-oxide-semiconductor (MOS) transistor comprising a double-level gate region, the double-level gate region comprising;

a floating gate overlying a channel region of the MOS transistor, the floating gate defining a gate of the MOS transistor;

a first gate dielectric disposed between the channel region and the floating gate;

a second gate dielectric overlying a portion of the floating gate;

a control gate disposed over the second gate dielectric; and

a first contact region in electrical contact with the floating gate, wherein the first contact region comprises a first metal track portion and a first contact via, wherein the first contact via physically contacts the first metal track portion and the floating gate, wherein a width of the first contact via is uniform along a length of the first contact via, wherein the width of the first contact via is less than a width of the first metal track portion, and wherein no portion of the second gate dielectric is disposed between the first metal track portion and the floating gate and no portion of the second gate dielectric physically contacts the first contact via; and

a capacitor having a first electrode defined by the floating gate of the double-level gate region of the MOS transistor, and a second electrode defined by the control gate of the double-level gate region of the MOS transistor.

9. The semiconductor structure of claim 8, further comprising a second contact region in electrical contact with the control gate, the first contact region and the second contact region being electrically isolated from one another.

10. The semiconductor structure of claim 9, wherein the second contact region comprises a second metal track portion coupled to the control gate by a second contact via.

11. The semiconductor structure of claim 10, wherein the first metal track portion and the second metal track portion are located in a same metallization level of an integrated circuit.

12. The semiconductor structure of claim 8, wherein the MOS transistor comprises a first one of a pair of transistors of a first inverter.

13. The semiconductor structure of claim 12, wherein the second electrode of the capacitor is electrically coupled to an output of a second inverter different from the first inverter.

14. The semiconductor structure of claim 13, wherein the floating gate of the double-level gate region of the MOS transistor comprises an input of the first inverter.

15. The semiconductor structure of claim 13, wherein the first inverter and the second inverter are cross-coupled inverters of an SRAM elementary memory cell.

16. A semiconductor structure, comprising:

a first dielectric layer disposed over an active region of a semiconductor substrate, the first dielectric layer having a first lateral dimension;

a first electrode disposed over the first dielectric layer, the first electrode being a gate of a first transistor and a first plate of a capacitor;

a second dielectric layer disposed over the first electrode, the second dielectric layer having a second lateral dimension less than the first lateral dimension;

a second electrode disposed over the second dielectric layer, the second electrode being a second plate of the capacitor; and

a first contact region in electrical contact with the first electrode, wherein the first contact region comprises a first metal track portion and a first contact via, wherein the first contact via physically contacts the first metal track portion and the first electrode, wherein a width of the first contact via is uniform along a length of the first contact via, wherein the width of the first contact via is less than a width of the first metal track portion, and wherein no portion of the second dielectric layer is disposed between the first metal track portion and the first electrode and no portion of the second dielectric layer physically contacts the first contact via.

17. The semiconductor structure of claim 16, wherein the first electrode has a lateral dimension substantially equal to the first lateral dimension of the first dielectric layer, and wherein the second electrode has a lateral dimension substantially equal to the second lateral dimension.

18. The semiconductor structure of claim 16, wherein the second plate of the capacitor is coupled to a second transistor different from the first transistor.

19. The semiconductor structure of claim 18, wherein the first transistor comprises a transistor of a first inverter, and wherein the second transistor comprises a transistor of a second inverter cross-coupled with the first inverter.

20. The semiconductor structure of claim 16, further comprising a second contact region in electrical contact with the second electrode, the first contact region and the second contact region being electrically isolated from one another.