Sense amplifier with negative threshold sensing for non-volatile memory

• US 10,304,550 B1
• Filed: 06/01/2018
• Issued: 05/28/2019
• Est. Priority Date: 11/29/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Nguyen, Hao, Lee, Seungpil
• Primary Examiner(s): Yang, Han
• Application Number:
  US15/995,517
• Publication Number:
  US 20190164616A1
• Time in Patent Office: 361 Days
• Field of Search: 36518521, 36518511, 365195, 365196
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. To reduce noise, a decoupling capacitor is connected to the control gate of the discharge transistor and an auxiliary keeper current is run through the discharge transistor.

Claims

1. An apparatus, comprising:

a discharge transistor;

a first discharge path configured to connect a selected bit line to the discharge transistor;

a second discharge path configured to connect a sense node to the discharge transistor; and

a biasing circuit configured to sense a memory cell connected to the selected bit line by setting a gate voltage on the discharge transistor by a voltage level on the first discharge path, subsequently cutting off the first discharge path while leaving the gate voltage on the discharge transistor to float at the voltage level and discharging the sense node through the discharge transistor by the second discharge path.

2. The apparatus of claim 1, further comprising:

a current source configured to provide a supplemental current through the discharge transistor, wherein the biasing circuit is further configured to turn on the current source to provide the supplemental current through the discharge transistor subsequent to cutting off the first discharge path and prior to discharging the sense node, and to continue to provide the supplemental current through the discharge transistor while discharging the sense node through the discharge transistor.

3. The apparatus of claim 1, further comprising:

a capacitor having a first plate connected to a gate of the discharge transistor, wherein the biasing circuit is further configured to apply a voltage level dependent on operating conditions to a second plate of the capacitor.

4. An apparatus, comprising:

a transistor;

a first switch and a second switch connected in series between a selected memory cell and the transistor, a control gate of the transistor connected to a node between the first switch and second switch, the first switch and second switch configured to discharge the selected memory cell through the transistor when concurrently on and configured to set the control gate of the transistor to float at a voltage level on the node between the first switch and second switch when the first switch and second switches are concurrently off, and

a third switch connected between a sense node and the transistor, the third switch configured to discharge the sense node through the transistor with the control gate of the transistor set to float at the voltage level on the node between the first switch and second switch.

5. The apparatus of claim 4, further comprising:

a supplemental current source configured to provide a supplemental current through the transistor subsequent to turning off the first and second switches and prior to turning on the third switch.

6. The apparatus of claim 4, further comprising:

a decoupling capacitor having a first plate connected to the control gate of the transistor.

7. The apparatus of claim 6, further comprising:

a biasing circuit configured to apply a voltage level dependent on operating conditions to a second plate of the decoupling capacitor subsequent to turning off the first and second switches and prior to turning on the third switch.

8. The apparatus of claim 4, further comprising:

a bit line, through which the selected memory cell is connected to the first and second switch;

a source line, the selected memory cell being connected between the source line and the bit line; and

a biasing circuit configured to set the source line to a higher voltage than the bit line during a sensing operation.

9. The apparatus of claim 8, further comprising:

a word line connected to a control gate of the selected memory cell, wherein the biasing circuit is configured to perform a sensing operation for a negative threshold voltage state by applying a non-negative voltage to the word line.

10. The apparatus of claim 9, wherein the biasing circuit is further configured to perform a sensing operation for positive threshold voltage state by discharging the bit line through the memory cell to the source line.

11. The apparatus of claim 4, wherein the apparatus comprises a memory array of a monolithic three-dimensional semiconductor memory device in which memory cells, including the selected memory cell, are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

12. The apparatus of claim 4, wherein the selected memory cell comprises a phase change memory material.

13. A method, comprising:

discharging a selected memory cell by a first discharge path through a sense amplifier;

setting a voltage on a control gate of a discharge transistor to a voltage level along the first discharge path, the voltage level dependent on a data state of the selected memory cell;

subsequently providing a supplemental current through the discharge transistor; and

while providing the supplemental current through the discharge transistor, discharging a sense node through the discharge transistor with the control gate of the discharge transistor set to the voltage level dependent on the data state of the selected memory cell.

14. The method of claim 13, further comprising:

providing the supplemental current to the discharge transistor through a clamp transistor through which the sense node is discharged; and

biasing the clamp transistor to maintain a constant voltage level on a node between the clamp transistor and the discharge transistor.

15. An apparatus, comprising:

a first transistor;

a first switch connected between a selected memory cell and a gate of the first transistor, the first switch configured to set a voltage level on the gate of the first transistor corresponding to a data state of the selected memory cell;

a second switch connected between a sense node and the first transistor and configured to discharge the sense node through the first transistor with the gate of the first transistors set to the voltage level corresponding to the data state of the selected memory cell; and

a current source configured to supply a supplemental current through the first transistor subsequent to setting the voltage level on the gate of the first transistor corresponding to the data state of the selected memory cell and prior to discharging the sense node through the first transistor.

16. The apparatus of claim 15, further comprising:

a bit line, through which the selected memory cell is connected to the first switch; and

a source line, the selected memory cell being connected between the source line and the bit line; and

a biasing circuit is configured to set the source line to a higher voltage than the bit line during a sensing operation.

17. The apparatus of claim 16, further comprising:

a word line connected to a control gate of the selected memory cell, wherein the biasing circuit is configured to perform a sensing operation for a negative threshold voltage state by applying a non-negative voltage to the word line.

18. The apparatus of claim 16, further comprising:

a word line connected to a control gate of the selected memory cell, wherein the biasing circuit is configured to perform a sensing operation for a plurality of threshold voltage states by applying one of a plurality of corresponding non-negative voltages to the word line.

19. The apparatus of claim 16, further comprising:

a second transistor through which the supplemental current is supplied to the first transistor and through which the sense node is discharged through the first transistor, wherein the biasing circuit is configured to maintain a constant voltage level on a node between the first and second transistors.

20. A sense amplifier circuit comprising:

a transistor connected to a discharge node;

means for discharging a selected memory cell through a discharge path of the sense amplifier circuit;

means for setting a control gate of the transistor to a voltage level dependent on a data state of the selected memory cell at a node of the discharge path while discharging the selected memory cell; and

means for discharging a sense node through the transistor while the control gate of the transistor is set at the voltage level dependent on the data state of the selected memory cell.