Method for manufacturing semiconductor device

• US 10,304,696 B2
• Filed: 04/20/2017
• Issued: 05/28/2019
• Est. Priority Date: 02/26/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koezuka, Junichi
• Primary Examiner(s): Seven, Evren
• Application Number:
  US15/492,483
• Publication Number:
  US 20170221933A1
• Time in Patent Office: 768 Days
• Field of Search: None
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 21/385 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

In a transistor including an oxide semiconductor layer, an oxide insulating layer is formed so as to be in contact with the oxide semiconductor layer. Then, oxygen is introduced (added) to the oxide semiconductor layer through the oxide insulating layer, and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, so that the oxide semiconductor layer is highly purified.

Claims

1. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer containing indium, gallium, and zinc;

a first electrode over the oxide semiconductor layer, the first electrode comprising a layer containing copper;

a second electrode over the oxide semiconductor layer, the second electrode comprising a layer containing copper;

a first metal oxide region in direct contact with a top surface and a side surface of the first electrode, the first metal oxide region containing copper;

a second metal oxide region in direct contact with a top surface and a side surface of the second electrode, the second metal oxide region containing copper;

an insulating layer over the first metal oxide region and the second metal oxide region, and in direct contact with the oxide semiconductor layer, the insulating layer containing silicon and oxygen; and

a pixel electrode over the insulating layer,

wherein the pixel electrode is in direct contact with the first electrode through an opening provided in the first metal oxide region and the insulating layer.

2. The semiconductor device according to claim 1, wherein the gate electrode has a stacked-layer structure of a layer containing titanium and a layer containing copper.

3. The semiconductor device according to claim 1, wherein the gate electrode comprises a layer containing titanium and a layer containing copper over the layer containing titanium.

4. The semiconductor device according to claim 1, wherein the gate insulating layer has a stacked-layer structure of a layer containing silicon and nitrogen and a layer containing silicon and oxygen.

5. The semiconductor device according to claim 1, wherein the gate insulating layer comprises a layer containing silicon and nitrogen and a layer containing silicon and oxygen over the layer containing silicon and nitrogen.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a depressed portion overlapping with the gate electrode.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a first region overlapping with the first electrode and the second electrode and a second region thinner than the first region.

8. The semiconductor device according to claim 1, wherein each of the first electrode and the second electrode has a stacked-layer structure of a layer containing titanium and the layer containing copper.

9. The semiconductor device according to claim 1, wherein each of the first electrode and the second electrode further comprises a layer containing titanium under the layer containing copper.

10. The semiconductor device according to claim 1, wherein the first metal oxide region and the second metal oxide region are formed by oxidizing the top surfaces and the side surfaces of the first electrode and the second electrode.

11. The semiconductor device according to claim 1, wherein the first metal oxide region and the second metal oxide region are formed when oxygen is introduced to the oxide semiconductor layer.

12. The semiconductor device according to claim 11, wherein the oxygen is introduced to the oxide semiconductor layer through the insulating layer.

13. The semiconductor device according to claim 1, further comprising a second insulating layer containing silicon and nitrogen over the insulating layer.

14. The semiconductor device according to claim 1, further comprising a liquid crystal layer over the pixel electrode.

15. The semiconductor device according to claim 14, further comprising a counter electrode over the liquid crystal layer.

16. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer containing indium, gallium, and zinc;

a first electrode over the oxide semiconductor layer, the first electrode comprising a layer containing copper;

a second electrode over the oxide semiconductor layer, the second electrode comprising a layer containing copper;

a first metal oxide region in direct contact with a surface of the first electrode, the first metal oxide region containing copper;

a second metal oxide region in direct contact with a surface of the second electrode, the second metal oxide region containing copper;

an insulating layer over the first metal oxide region and the second metal oxide region, and in direct contact with the oxide semiconductor layer, the insulating layer containing silicon and oxygen; and

a pixel electrode over the insulating layer,

wherein the pixel electrode is in direct contact with the first electrode in a portion where the first metal oxide region is not provided.

17. The semiconductor device according to claim 16, wherein the gate electrode has a stacked-layer structure of a layer containing titanium and a layer containing copper.

18. The semiconductor device according to claim 16, wherein the gate electrode comprises a layer containing titanium and a layer containing copper over the layer containing titanium.

19. The semiconductor device according to claim 16, wherein the gate insulating layer has a stacked-layer structure of a layer containing silicon and nitrogen and a layer containing silicon and oxygen.

20. The semiconductor device according to claim 16, wherein the gate insulating layer comprises a layer containing silicon and nitrogen and a layer containing silicon and oxygen over the layer containing silicon and nitrogen.

21. The semiconductor device according to claim 16, wherein the oxide semiconductor layer comprises a depressed portion overlapping with the gate electrode.

22. The semiconductor device according to claim 16, wherein the oxide semiconductor layer comprises a first region overlapping with the first electrode and the second electrode and a second region thinner than the first region.

23. The semiconductor device according to claim 16, wherein each of the first electrode and the second electrode comprises a conductive metal oxide containing at least one of indium, tin, and zinc.

24. The semiconductor device according to claim 16, wherein each of the first electrode and the second electrode has a stacked-layer structure of a layer containing titanium and the layer containing copper.

25. The semiconductor device according to claim 16, wherein each of the first electrode and the second electrode further comprises a layer containing titanium under the layer containing copper.

26. The semiconductor device according to claim 16, wherein the first metal oxide region and the second metal oxide region are formed by oxidizing the surfaces of the first electrode and the second electrode.

27. The semiconductor device according to claim 16, wherein the first metal oxide region and the second metal oxide region are formed when oxygen is introduced to the oxide semiconductor layer.

28. The semiconductor device according to claim 27, wherein the oxygen is introduced to the oxide semiconductor layer through the insulating layer.

29. The semiconductor device according to claim 23, further comprising a second insulating layer containing silicon and nitrogen over the insulating layer.

30. The semiconductor device according to claim 23, further comprising a liquid crystal layer over the pixel electrode.

31. The semiconductor device according to claim 30, further comprising a counter electrode over the liquid crystal layer.

32. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer containing indium, gallium, and zinc;

a first conductive layer over the oxide semiconductor layer, the first conductive layer containing titanium;

a second conductive layer over and in direct contact with the first conductive layer, the second conductive layer containing copper;

a third conductive layer over the oxide semiconductor layer, the third conductive layer containing titanium;

a fourth conductive layer over and in direct contact with the third conductive layer, the fourth conductive layer containing copper;

a first metal oxide region covering the second conductive layer, the first metal oxide region containing copper;

a second metal oxide region covering the fourth conductive layer, the second metal oxide region containing copper;

an insulating layer over the first metal oxide region and the second metal oxide region, and in direct contact with the oxide semiconductor layer, the insulating layer containing silicon and oxygen; and

a pixel electrode over the insulating layer,

wherein the pixel electrode is in direct contact with the second conductive layer through an opening provided in the first metal oxide region and the insulating layer.

33. The semiconductor device according to claim 32, wherein the gate electrode has a stacked-layer structure of a layer containing titanium and a layer containing copper.

34. The semiconductor device according to claim 32, wherein the gate electrode comprises a layer containing titanium and a layer containing copper over the layer containing titanium.

35. The semiconductor device according to claim 32, wherein the gate insulating layer has a stacked-layer structure of a layer containing silicon and nitrogen and a layer containing silicon and oxygen.

36. The semiconductor device according to claim 32, wherein the gate insulating layer comprises a layer containing silicon and nitrogen and a layer containing silicon and oxygen over the layer containing silicon and nitrogen.

37. The semiconductor device according to claim 32, wherein the oxide semiconductor layer comprises a depressed portion overlapping with the gate electrode.

38. The semiconductor device according to claim 32, wherein the oxide semiconductor layer comprises a first region overlapping with the first conductive layer and the third conductive layer and a second region thinner than the first region.

39. The semiconductor device according to claim 32, wherein the first metal oxide region and the second metal oxide region are formed by oxidizing surfaces of the second conductive layer and the fourth conductive layer.

40. The semiconductor device according to claim 32, wherein the first metal oxide region and the second metal oxide region are formed when oxygen is introduced to the oxide semiconductor layer.

41. The semiconductor device according to claim 40, wherein the oxygen is introduced to the oxide semiconductor layer through the insulating layer.

42. The semiconductor device according to claim 32, further comprising a second insulating layer containing silicon and nitrogen over the insulating layer.

43. The semiconductor device according to claim 32, further comprising a liquid crystal layer over the pixel electrode.

44. The semiconductor device according to claim 43, further comprising a counter electrode over the liquid crystal layer.

45. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer containing indium, gallium, and zinc;

a first conductive layer over the oxide semiconductor layer, the first conductive layer containing titanium;

a second conductive layer over and in direct contact with the first conductive layer, the second conductive layer containing copper;

a third conductive layer over the oxide semiconductor layer, the third conductive layer containing titanium;

a fourth conductive layer over and in direct contact with the third conductive layer, the fourth conductive layer containing copper;

a first metal oxide region covering the second conductive layer, the first metal oxide region containing copper;

a second metal oxide region covering the fourth conductive layer, the second metal oxide region containing copper;

an insulating layer over the first metal oxide region and the second metal oxide region, and in direct contact with the oxide semiconductor layer, the insulating layer containing silicon and oxygen; and

a pixel electrode over the insulating layer,

wherein the pixel electrode is in direct contact with the second conductive layer in a portion where the first metal oxide region is not provided.

46. The semiconductor device according to claim 45, wherein the gate electrode has a stacked-layer structure of a layer containing titanium and a layer containing copper.

47. The semiconductor device according to claim 45, wherein the gate electrode comprises a layer containing titanium and a layer containing copper over the layer containing titanium.

48. The semiconductor device according to claim 45, wherein the gate insulating layer has a stacked-layer structure of a layer containing silicon and nitrogen and a layer containing silicon and oxygen.

49. The semiconductor device according to claim 45, wherein the gate insulating layer comprises a layer containing silicon and nitrogen and a layer containing silicon and oxygen over the layer containing silicon and nitrogen.

50. The semiconductor device according to claim 45, wherein the oxide semiconductor layer comprises a depressed portion overlapping with the gate electrode.

51. The semiconductor device according to claim 45, wherein the oxide semiconductor layer comprises a first region overlapping with the first conductive layer and the third conductive layer and a second region thinner than the first region.

52. The semiconductor device according to claim 45, wherein the first metal oxide region and the second metal oxide region are formed by oxidizing surfaces of the second conductive layer and the fourth conductive layer.

53. The semiconductor device according to claim 45, wherein the first metal oxide region and the second metal oxide region are formed when oxygen is introduced to the oxide semiconductor layer.

54. The semiconductor device according to claim 53, wherein the oxygen is introduced to the oxide semiconductor layer through the insulating layer.

55. The semiconductor device according to claim 45, further comprising a second insulating layer containing silicon and nitrogen over the insulating layer.

56. The semiconductor device according to claim 45, further comprising a liquid crystal layer over the pixel electrode.

57. The semiconductor device according to claim 56, further comprising a counter electrode over the liquid crystal layer.