Integrated circuit having a vertical power MOS transistor

• US 10,304,829 B2
• Filed: 11/02/2017
• Issued: 05/28/2019
• Est. Priority Date: 07/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Su, Po-Chih, Liu, Ruey-Hsin
• Primary Examiner(s): Vu, David
• Application Number:
  US15/801,724
• Publication Number:
  US 20180151569A1
• Time in Patent Office: 572 Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A device includes a vertical transistor and a lateral transistor on a substrate, wherein the vertical transistor comprises a first gate in a first trench, a second gate in a second trench, a source and a drain, wherein the source and the drain are on opposite sides of the first trench and the lateral transistor and the drain are on opposite sides of the second trench.

Claims

1. A device comprising:

a vertical transistor comprising;

a first gate in a first trench, wherein a dielectric layer and a gate region are in the first trench;

a second gate in a second trench, wherein a bottom of the second trench is lower than a bottom of the gate region;

a first drain/source region and a second drain/source region formed on opposite sides of the first trench; and

a first lateral transistor, wherein the first later transistor and the second drain/source region are on opposite sides of the second trench.

2. The device of claim 1, wherein:

the first lateral transistor is between a first isolation region and a second isolation region.

3. The device of claim 2, further comprising:

a third isolation region between the first isolation region and the second isolation region, wherein a first drain/source region of the first lateral transistor extends from a sidewall of the third isolation region to a sidewall of the second isolation region.

4. The device of claim 3, wherein:

the first isolation region is between the second trench and a second drain/source region of the first lateral transistor.

5. The device of claim 4, wherein:

the first lateral transistor is in a semiconductor structure having a first buried layer over a substrate, a first well over the first buried layer and a second well in the first well, and wherein;

three sides of the second well are surrounded by the first well; and

a width of the first buried layer is substantially equal to a width of the first well.

6. The device of claim 5, wherein:

the first drain/source region of the first lateral transistor is in the first well; and

the second drain/source region of the first lateral transistor is in the second well.

7. The device of claim 5, wherein:

a bottommost surface of the first well is higher than a bottommost surface of the second gate.

8. The device of claim 5, wherein:

the first trench extends through a high voltage well and partially through a buried layer, and wherein the high voltage well is over the buried layer.

9. The device of claim 1, wherein:

a bottommost surface of the gate region is over a topmost surface of the dielectric layer, and wherein the gate region and the dielectric layer form the first gate;

a width of the second trench is greater than a width of the first trench; and

a bottom of the first trench is substantially level with a bottom of the second trench.

10. A device comprising:

a vertical transistor comprising;

a first gate in a first trench, wherein the first gate comprises a dielectric layer and a first conductive region over the dielectric layer;

a second gate in a second trench, wherein a bottom of the second trench is substantially level with a bottom surface of the first trench, and wherein the second gate comprises a second conductive region having a bottom lower than a bottom of the first conductive region;

a source region and a drain region formed on opposite sides of the first trench; and

a plurality of lateral transistors, wherein the plurality of lateral transistors and the drain region are on opposite sides of the second trench.

11. The device of claim 10, wherein:

two adjacent lateral transistors are separated by an isolation region.

12. The device of claim 10, wherein:

the plurality of lateral transistors includes a high voltage lateral transistor and a low voltage lateral transistor.

13. The device of claim 12, wherein:

a drain/source region of the high voltage lateral transistor extends from a sidewall of a first isolation region to a sidewall of a second isolation region, and wherein a bottom of the drain/source region of the high voltage lateral transistor is higher than bottoms of the first isolation region and the second isolation region.

14. The device of claim 12, wherein:

the high voltage lateral transistor and the low voltage lateral transistor are formed in two different wells over a substrate.

15. The device of claim 10, wherein:

a sidewall of the source region is in contact with a sidewall of the first trench; and

a sidewall of the drain region is in contact with a sidewall of the second trench.

16. A device comprising:

a vertical transistor and a lateral transistor on a substrate, wherein;

the vertical transistor comprises a first gate in a first trench, a second gate in a second trench, a source and a drain, wherein the source and the drain are on opposite sides of the first trench, and wherein a depth of the second gate is greater than a depth of the first gate; and

the lateral transistor and the drain are on opposite sides of the second trench.

17. The device of claim 16, wherein:

the vertical transistor is formed in a first semiconductor structure including a first buried layer over the substrate, a first well over the first buried layer, and wherein the first trench and the second trench extend through the first well and partially through the first buried layer.

18. The device of claim 17, wherein:

the first gate is in an upper portion of the first trench; and

the second gate extends through the second trench, and wherein a bottom of the first gate is higher than a bottom of the second gate.

19. The device of claim 17, wherein:

the lateral transistor is formed in a second semiconductor structure including a second buried layer over the substrate, a second well over the second buried layer, and wherein a width of the second well is substantially equal to a width of the second buried layer.

20. The device of claim 19, wherein:

a bottom of the second buried layer is substantially level with a bottom of the first buried layer; and

a bottom of the second well is substantially level with a bottom of the first well.