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Pads and pin-outs in three dimensional integrated circuits

  • US 10,304,854 B2
  • Filed: 05/21/2018
  • Issued: 05/28/2019
  • Est. Priority Date: 11/19/2007
  • Status: Active Grant
First Claim
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1. A method, comprising:

  • forming a programmable layer of a hard-wired device by using a plurality of first masks in common with a programmable device fabrication process;

    forming a hard-wire layer of the hard-wired device by using a plurality of second masks omitted from the programmable device fabrication process, wherein the hard-wire layer is operable to hard-wire the programmable layer with a logical functionality; and

    forming a pad layer of the hard-wired device by using a plurality of third masks in common with the programmable device fabrication process.

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