Pads and pin-outs in three dimensional integrated circuits

• US 10,304,854 B2
• Filed: 05/21/2018
• Issued: 05/28/2019
• Est. Priority Date: 11/19/2007
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US15/985,590
• Publication Number:
  US 20180277549A1
• Time in Patent Office: 372 Days
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.

Claims

1. A method, comprising:

forming a programmable layer of a hard-wired device by using a plurality of first masks in common with a programmable device fabrication process;

forming a hard-wire layer of the hard-wired device by using a plurality of second masks omitted from the programmable device fabrication process, wherein the hard-wire layer is operable to hard-wire the programmable layer with a logical functionality; and

forming a pad layer of the hard-wired device by using a plurality of third masks in common with the programmable device fabrication process.

2. The method of claim 1, further comprising:

forming an interconnect layer of the hard-wired device by using a plurality of fourth masks in common with the programmable device fabrication process.

3. The method of claim 1, further comprising:

forming an interconnect layer of the hard-wired device by using a plurality of masks that modify a characteristic associated with the programmable device fabrication process.

4. The method of claim 3, wherein the characteristic comprises one of a timing characteristic or a power characteristic.

5. The method of claim 1, further comprising:

using a first semiconductor die to perform said forming a programmable layer;

using a second semiconductor die to perform said forming a hard-wire layer;

flipping the second semiconductor die to couple a top side of the second semiconductor die to the first semiconductor die to form a stacked arrangement; and

using the stacked arrangement to perform said forming a pad layer.

6. The method of claim 5, wherein said flipping the second semiconductor die comprises one of:

bonding the top side of the second semiconductor die to a top side of the first semiconductor die;

or

gluing the top side of the second semiconductor die to the top side of the first semiconductor die.

7. The method of claim 5, wherein said using the stacked arrangement comprises removing material from a bottom side of the second semiconductor die.

8. A method, comprising:

forming a plurality of layers of a hard-wired device by using a first plurality of masks in common with a programmable device fabrication process, wherein said forming a plurality of layers includes;

forming a programmable layer; and

forming a pad layer; and

forming a hard-wire layer of the hard-wired device by using a second plurality of masks omitted from the programmable device fabrication process, wherein the hard-wire layer is operable to hard-wire the programmable layer with a logical functionality.

9. The method of claim 8, further comprising:

forming an interconnect layer of the hard-wired device by using a third plurality of masks in common with the programmable device fabrication process.

10. The method of claim 8, further comprising:

forming an interconnect layer of the hard-wired device by using a plurality of masks that modify a characteristic associated with the programmable device fabrication process.

11. The method of claim 10, wherein the characteristic comprises one of a timing characteristic or a power characteristic.

12. The method of claim 8, further comprising:

using a first semiconductor die to perform said forming a programmable layer;

using a second semiconductor die to perform said forming a hard-wire layer;

flipping the second semiconductor die to couple a top side of the second semiconductor die to the first semiconductor die to form a stacked arrangement; and

using the stacked arrangement to perform said forming a pad layer.

13. The method of claim 12, wherein said flipping the second semiconductor die comprises one of:

bonding the top side of the second semiconductor die to a top side of the first semiconductor die;

or

gluing the top side of the second semiconductor die to the top side of the first semiconductor die.

14. The method of claim 12, wherein said using the stacked arrangement comprises removing material from a bottom side of the second semiconductor die.

15. A method, comprising:

forming a hard-wired device operable to provide a logical functionality in common with a programmable device fabrication process, wherein said forming a hard-wired device includes;

using a plurality of first masks in common with the programmable device fabrication process to form a programmable layer;

using a plurality of second masks omitted from the programmable device fabrication process to form a hard-wire layer operable to hard-wire the programmable layer with the logical functionality; and

using a plurality of third masks in common with the programmable device fabrication process to form a pad layer.

16. The method of claim 15, wherein said forming a hard-wired device further comprises:

using a plurality of fourth masks in common with the programmable device fabrication process to form an interconnect layer.

17. The method of claim 15, wherein said forming a hard-wired device further comprises:

using a plurality of masks that modify a characteristic associated with the programmable device fabrication process to form an interconnect layer.

18. The method of claim 17, wherein the characteristic comprises one of a timing characteristic or a power characteristic.

19. The method of claim 15, wherein said forming a hard-wired device further comprises:

using a first semiconductor die to form the programmable layer;

using a second semiconductor die to form the hard-wire layer;

flipping the second semiconductor die to couple a top side of the second semiconductor die to the first semiconductor die to form a stacked arrangement; and

using the stacked arrangement to form the pad layer.

20. The method of claim 19, wherein said using the stacked arrangement comprises removing material from a bottom side of the second semiconductor die, and wherein said flipping the second semiconductor die comprises one of:

bonding the top side of the second semiconductor die to a top side of the first semiconductor die;

or

gluing the top side of the second semiconductor die to the top side of the first semiconductor die.