Fault attack protection against synchronized fault injections

• US 10,305,479 B1
• Filed: 06/12/2018
• Issued: 05/28/2019
• Est. Priority Date: 06/12/2018
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Doll, Stefan, Regner, Markus, Jain, Sandeep
• Primary Examiner(s): Houston, Adam D
• Application Number:
  US16/006,457
• Time in Patent Office: 350 Days
• CPC Class Codes: H03K 19/003 Modifications for increasing the reliability for protection
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H04L 9/004 for fault attacks

Abstract

Various embodiments relate to a circuit, including: a first secure circuit configured to receive an input and to produce a first output; a first delay circuit configured to receive the first output and to produce a first delayed output delayed by a time N; a second delay circuit configured to receive the input and to produce a delayed input delayed by a time N; a second secure circuit configured to receive the delayed input and to produce a second delayed output; and a comparator configured to compare the first delayed output to the second delayed output and to produce a result, wherein the result is one of the first delayed output or second delayed output when the first delayed output matches the second delayed output and the result is an error value when the first delayed output does not match the second delayed output.

Claims

1. A circuit, comprising:

a first secure circuit configured to receive an input and to produce a first output;

a first delay circuit configured to receive the first output and to produce a first delayed output delayed by a time N;

a second delay circuit configured to receive the input and to produce a delayed input delayed by a time N;

a second secure circuit configured to receive the delayed input and to produce a second delayed output; and

a comparator configured to compare the first delayed output to the second delayed output and to produce a result, wherein the result is one of the first delayed output or second delayed output when the first delayed output matches the second delayed output and the result is an error value when the first delayed output does not match the second delayed output.

2. The circuit of claim 1, wherein the value of N is randomly selected.

3. The circuit of claim 1, wherein the value of N is periodically changed.

4. The circuit of claim 1, further comprising:

a third delay circuit configured to receive the result and to produce a delayed result delayed by a time M.

5. The circuit of claim 4, wherein the value of N is randomly selected and the value of M=x−

N where x is a constant total delay value.

6. The circuit of claim 5, wherein the value of N and M are periodically changed.

7. A method of securely producing an output by a circuit, comprising:

receiving an input by a first secure circuit and producing a first output;

receiving the output by a first delay circuit and producing a first delayed output delayed by a time N;

receiving the input by a second delay circuit and producing a delayed input delayed by a time N;

receiving the delayed input by a second secure circuit and producing a second delayed output; and

comparing by a comparator the first delayed output to the second delayed output and producing a result, wherein the result is one of the first delayed output or second delayed output when the first delayed output matches the second delayed output and the result is an error value when the first delayed output does not match the second delayed output.

8. The method of claim 7, wherein the value of N is randomly selected.

9. The method of claim 7, wherein the value of N is periodically changed.

10. The method of claim 7, further comprising:

receiving the result by a third delay circuit and producing a delayed result delayed by a time M.

11. The method of claim 10, wherein the value of N is randomly selected and the value of M=x−

N where x is a constant total delay value.

12. The method of claim 11, wherein the value of N and M are periodically changed.

13. A circuit, comprising:

a first delay circuit configured to receive an input and to produce a first delayed input delayed by a time a·

N, where N is a time delay and a is a scalar value from 0 to n;

a second delay circuit configured to receive the input and to produce a second delayed input delayed by a time b·

N, where b is a scalar value from 0 to n;

a third delay circuit configured to receive the input and to produce a third delayed input delayed by a time c·

N, where c is a scalar value from 0 to n;

a first secure circuit configured to receive the first delayed input and to produce a first delayed output;

a second secure circuit configured to receive the second delayed input and to produce a second delayed output;

a third secure circuit configured to receive the third delayed input and to produce a third delayed output;

a fourth delay circuit configured to receive the first delayed output and to produce a fourth delayed output delayed by a time (n-a)·

N;

a fifth delay circuit configured to receive the second delayed output and to produce a fifth delayed output delayed by a time (n-b)·

N;

a sixth delay circuit configured to receive the third delayed output and to produce a sixth delayed output delayed by a time (n-c)·

N; and

a comparator configured to compare the fourth delayed output, the fifth delayed output, and sixth delayed output and to produce a result, wherein the result is one of the fourth delayed output, fifth delayed output, or second delayed output when the fourth delayed output, the fifth delayed output, and sixth delayed output are all equal to one another and the result is an error value otherwise.

14. The circuit of claim 13, wherein the value of N is randomly selected.

15. The circuit of claim 13, wherein the value of N is periodically changed.

16. The circuit of claim 13, further comprising:

a third delay circuit configured to receive the result and to produce a delayed result delayed by a time M.

17. The circuit of claim 16, wherein the value of N is randomly selected and the value of M=x−

N where x is a constant total delay value.

18. The circuit of claim 17, wherein the value of N and M are periodically changed.

19. The circuit of claim 17, wherein at least two of the scalar values a, b, and c are different.