Phase control of clock signal based on feedback
First Claim
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1. A data converter system with clock signal phase adjustment, the data converter system comprising:
- a first data converter configured to receive a clock signal and to provide a feedback signal, wherein a phase associated with the first data converter is based on the clock signal;
a second data converter; and
a clock generator in communication with the first data converter and the second data converter, the clock generator configured to provide the clock signal, the clock generator comprising;
a feedback signal processor configured to receive the feedback signal from the first data converter and to compute a phase control signal based on the feedback signal; and
a clock generating circuit configured to adjust the phase of the clock signal based on the phase control signal for synchronizing the first data converter with the second converter at corresponding nodes of the first data converter and the second data converter.
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Abstract
Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.
165 Citations
22 Claims
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1. A data converter system with clock signal phase adjustment, the data converter system comprising:
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a first data converter configured to receive a clock signal and to provide a feedback signal, wherein a phase associated with the first data converter is based on the clock signal; a second data converter; and a clock generator in communication with the first data converter and the second data converter, the clock generator configured to provide the clock signal, the clock generator comprising; a feedback signal processor configured to receive the feedback signal from the first data converter and to compute a phase control signal based on the feedback signal; and a clock generating circuit configured to adjust the phase of the clock signal based on the phase control signal for synchronizing the first data converter with the second converter at corresponding nodes of the first data converter and the second data converter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A feedback signal processor for providing a phase control signal for adjusting a phase of a clock signal, the feedback signal processor comprising:
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a phase processor comprising a time-to-digital converter, the phase processor configured to; receive a feedback signal generated by a device that is configured to receive a clock signal; and generate a digital signal indicative of a phase of the feedback signal relative to a phase of another signal, wherein the phase of the feedback signal depends on the clock signal; and a calculation circuit configured to compute a phase control signal based on the digital signal and to output the phase control signal for adjusting the phase of the clock signal. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A clock generator system with clock signal phase adjustment, the clock generator system comprising:
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a first clock generator comprising; means for generating a phase control signal based on feedback from a device configured to receive a clock signal from the clock generator system; a clock generating circuit configured to generate the clock signal, adjust a phase of the clock signal based on the phase control signal, and output the clock signal having an adjusted phase; and a second clock generator configured to receive a feedback signal from the first clock generator, the second clock generator comprising; a second clock generating circuit configured to generate a second clock signal, adjust a phase of the second clock signal based on the feedback signal from the first clock generator, and output the second clock signal having a second adjusted phase. - View Dependent Claims (22)
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Specification