System and method for encoding using multiple linear feedback shift registers
First Claim
1. A method for encoding a first stream of bits, comprising:
- splitting with one or more switches, a first input stream of bits to multiple second streams;
encoding, in parallel and by using multiple linear feedback shift register (LSFR) circuits, the multiple second streams to provide third streams, wherein each second stream of the multiple second streams is encoded using an LFSR circuit of the multiple LFSR circuits;
wherein the encoding comprises feeding the multiple second streams to the multiple LFSR circuits;
merging, with memory cells, the third streams to provide a fourth stream;
wherein the fourth stream is stored in the multiple LFSR circuits; and
encoding the fourth stream to provide a fifth stream;
wherein the encoding of the fourth stream comprises concatenating the multiple LFSR circuits while bypassing feedback circuits of some of the multiple LFSR circuits; and
shifting the fourth stream through the multiple LFSR circuits.
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Accused Products
Abstract
An encoder and a method for encoding a first stream of bits, the method may include splitting the first stream of bits to multiple second streams; encoding, in parallel and by using multiple linear feedback shift registers (LFSRs), the multiple second streams to provide third streams, wherein each second stream of the multiple second streams is encoded using an LFSR of the multiple LFSRs; wherein the encoding comprises feeding the multiple second streams to the multiple LFSRs; merging the third streams to provide a fourth stream; wherein the fourth stream is stored in the multiple LFSRs; and encoding the fourth stream to provide a fifth stream; wherein the encoding of the fourth stream comprises concatenating the multiple LFSRs while bypassing feedback circuits of some of the multiple LFSRs; and shifting the fourth stream through the multiple LFSRs.
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Citations
20 Claims
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1. A method for encoding a first stream of bits, comprising:
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splitting with one or more switches, a first input stream of bits to multiple second streams; encoding, in parallel and by using multiple linear feedback shift register (LSFR) circuits, the multiple second streams to provide third streams, wherein each second stream of the multiple second streams is encoded using an LFSR circuit of the multiple LFSR circuits;
wherein the encoding comprises feeding the multiple second streams to the multiple LFSR circuits;merging, with memory cells, the third streams to provide a fourth stream;
wherein the fourth stream is stored in the multiple LFSR circuits; andencoding the fourth stream to provide a fifth stream;
wherein the encoding of the fourth stream comprises concatenating the multiple LFSR circuits while bypassing feedback circuits of some of the multiple LFSR circuits; andshifting the fourth stream through the multiple LFSR circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An encoder implemented on one or more integrated circuit devices for encoding a first stream of bits, comprising:
multiple linear feedback shift register (LSFR) circuits; logic, coupled to the multiple LFSR circuits, wherein the logic is configured to; split, with one or more switches, the first stream of bits to multiple second streams; and feed the multiple second streams to the multiple LFSR circuits in parallel; wherein the multiple LFSR circuits are configured to encode, in parallel, the multiple second streams to provide third streams, wherein each second stream of the multiple second streams is encoded using an LFSR circuit of the multiple LFSR circuits; wherein the logic is configured to; merge the third streams to provide a fourth stream;
wherein the fourth stream is stored in memory cells of the multiple LFSR circuits; andconcatenate the multiple LFSR circuits while bypassing feedback circuits of some of the multiple LFSR circuits; wherein at least one of the multiple LFSR circuits is configured to encode the fourth stream to provide a fifth stream; wherein the logic is configured to shift the fourth stream through memory cells of the multiple LFSR circuits during the encoding of the fourth stream. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
Specification