Apparatus for receiver with digital signal arrival detector and associated methods

• US 10,305,676 B2
• Filed: 05/29/2016
• Issued: 05/28/2019
• Est. Priority Date: 07/24/2013
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: de Ruijter, Hendricus, Xiong, Ping, Li, Wentao, Zhou, Yan
• Primary Examiner(s): Cadeau, Wednel
• Application Number:
  US15/168,080
• Publication Number:
  US 20160277177A1
• Time in Patent Office: 1,094 Days
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 17/318 Received signal strength
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04J 3/1605 Fixed allocated frame structures
• CPC Class Codes: H04L 1/206 for modulated signals
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04W 56/00 Synchronisation arrangements

Abstract

An apparatus includes a radio frequency (RF) receiver, which includes a digital signal arrival (DSA) detector to detect arrival of a transmitted signal. The DSA detector includes a signal correlator and at least one of (a) an absolute received signal strength indication (RSSI) detector; (b) a relative RSSI detector; and (c) a frequency offset detector). The RF receiver further includes a demodulator coupled to the DSA detector to demodulate a received signal and to provide a demodulated signal, and a synchronization word detector (SWD) coupled to the demodulator to receive the demodulated signal.

Claims

1. An apparatus comprising:

a radio frequency (RF) receiver comprising;

a digital signal arrival (DSA) detector to detect arrival of a transmitted signal, the DSA detector comprising a signal correlator coupled to a relative received signal strength indication (RSSI) detector;

a demodulator coupled to the DSA detector to demodulate a received signal and to provide a demodulated signal;

a synchronization word detector (SWD) coupled to the demodulator to receive the demodulated signal; and

a controller, wherein the relative RSSI detector provides a first detect signal to the controller when a current RSSI value exceeds a sum of a threshold and an earlier RSSI value.

2. The apparatus according to claim 1, wherein the DSA detector comprises an absolute RSSI detector, and wherein the absolute RSSI detector provides a detect signal to the controller when an RSSI value exceeds a threshold.

3. The apparatus according to claim 1, wherein the controller uses the detect signal to qualify, start, or enable operation of the signal correlator.

4. The apparatus according to claim 1, wherein the controller uses the first detect signal to qualify or enable operation of the signal correlator.

5. The apparatus according to claim 1, wherein the relative RSSI detector provides a second detect signal to the controller, wherein the second detect signal is derived from an updated earlier RSSI value.

6. The apparatus according to claim 1, wherein the relative RSSI detector comprises a finite impulse response (FIR) filter coupled to first and second adders, wherein the FIR filter receives an RSSI value, and the first and second adders provide the current and earlier RSSI values, respectively.

7. The apparatus according to claim 1, wherein the DSA detector further comprises an absolute RSSI detector, and/or (c) a frequency offset detector.

8. The apparatus according to claim 6, wherein the relative RSSI detector further comprises:

a third adder to add the earlier RSSI value and the threshold to provide a sum; and

a comparator to provide the first detect signal to the controller when a current RSSI value exceeds the sum.

9. An integrated circuit (IC), comprising:

a radio frequency (RF) receiver, comprising;

a controller;

a signal correlator coupled to the controller, the signal correlator to detect arrival of a signal and to provide a first detect signal to the controller;

a received signal strength indication (RSSI) detector coupled to the controller to provide at least one detect signal to the controller in response to a digital in-phase (I) signal and a digital quadrature (Q) signal derived from a received radio frequency (RF) signal, wherein the RSSI detector further comprises a relative RSSI detector to provide a second detect signal to the controller when a current RSSI value exceeds a sum of a threshold and an earlier RSSI value; and

a frequency offset detector coupled to the controller to provide a frequency error signal to the controller.

10. The IC according to claim 9, wherein the RSSI detector comprises an absolute RSSI detector to provide a third detect signal to the controller when an RSSI value exceeds a first threshold.

11. The IC according to claim 9, wherein the controller uses the first detect signal to qualify or enable operation of the signal correlator.

12. The IC according to claim 9, wherein the relative RSSI detector comprises:

a finite impulse response (FIR) filter coupled to first and second adders, wherein the FIR filter receives an RSSI value, and the first and second adders provide the current and earlier RSSI values, respectively;

a third adder to add the earlier RSSI value and the threshold to provide a sum; and

a comparator to provide the first detect signal to the controller when a current RSSI value exceeds the sum.

13. The IC according to claim 10, wherein the relative RSSI detector provides a fourth detect signal to the controller, wherein the fourth detect signal is derived from an updated earlier RSSI value.

14. The IC according to claim 13, wherein the controller uses at least one of the first, second, third, and fourth detect signals to receive transmitted information.

15. A method of receiving radio frequency (RF) signals, the method comprising:

detecting, by using a digital signal arrival detector, arrival of a transmitted signal, by using a signal correlator, and a relative RSSI detector to provide a first detect signal when a current RSSI value exceeds a sum of a threshold and an earlier RSSI value;

demodulating the transmitted signal to provide a demodulated signal; and

detecting a synchronization word in the demodulated signal.

16. The method according to claim 15, wherein the digital signal arrival detector includes an absolute RSSI detector, the method further comprising using the absolute RSSI detector to provide a second detect signal when an RSSI value exceeds a threshold.

17. The method according to claim 15, further comprising qualifying or enabling operation of the signal correlator by using the first detect signal.

18. The method according to claim 15, further comprising using the relative RSSI detector to provide a third detect signal, wherein the third detect signal is derived from an updated earlier RSSI value.

19. The method according to claim 15, wherein detecting, by using the digital signal arrival detector, arrival of the transmitted signal, further comprises using an absolute RSSI detector and/or a frequency offset detector.

20. The method according to claim 16, further comprising qualifying, starting, or enabling operation of the signal correlator by using the second detect signal.