Circuit board and method for manufacturing a circuit board

• US 10,306,750 B2
• Filed: 12/10/2015
• Issued: 05/28/2019
• Est. Priority Date: 12/11/2014
• Status: Active Grant

• Current Assignee: AT&S Austria Technologie & Systemtechnik AG
• Original Assignee: AT&S Austria Technologie & Systemtechnik AG
• Inventors: Stahr, Hannes, Zluc, Andreas, Schwarz, Timo, Weidinger, Gerald
• Primary Examiner(s): Dinh, Tuan T
• Application Number:
  US15/534,172
• Publication Number:
  US 20170339783A1
• Time in Patent Office: 1,265 Days
• Field of Search: 361760-766, 361790-795, 174258-268, 257660-760
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3511 Warping
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 1/0353 : consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
• CPC Class Codes: H05K 1/0366 : reinforced, e.g. by fibres, fabrics H05K1/036 takes precedence
• CPC Class Codes: H05K 1/0373 : containing additives, e.g. fillers H05K1/036 takes precedence
• CPC Class Codes: H05K 1/0393 : Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups
• CPC Class Codes: H05K 1/115 : Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 1/189 : characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 2201/0129 : Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
• CPC Class Codes: H05K 2201/0133 : Elastomeric or compliant polymer elastomeric conductor H05K2201/0314
• CPC Class Codes: H05K 2201/0187 : with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
• CPC Class Codes: H05K 2201/0191 : wherein the thickness of the dielectric plays an important role
• CPC Class Codes: H05K 2201/068 : wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/09136 : Means for correcting warpage
• CPC Class Codes: H05K 2203/1536 : Temporarily stacked PCBs
• CPC Class Codes: H05K 3/0017 : Etching of the substrate by chemical or physical means
• CPC Class Codes: H05K 3/0097 : Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards H05K3/0052 takes precedence
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A circuit board and a method of manufacturing a circuit board or two circuit boards are illustrated and described. The circuit board includes (a) a dielectric layer with a planar extension in parallel with respect to an xy-plane which is spanned by an x-axis and a y-axis perpendicular thereto and a layer thickness along a z-direction which is perpendicular with respect to the x-axis and to the y-axis; (b) a metallic layer which is attached to the dielectric layer in a planar manner; and (c) a component which is embedded in the dielectric layer and/or in a dielectric core-layer of the circuit board. The dielectric layer includes a dielectric material which has (i) an elastic modulus E in a range between 1 and 20 GPa and (ii) a coefficient of thermal expansion in a range between 0 and 17 ppm/K along the x-axis and along the y-axis.

Claims

1. A circuit board, comprising:

a dielectric layer which comprises

a planar extension in parallel with respect to an xy-plane which is spanned by an x-axis and a y-axis perpendicular thereto, and

a layer thickness along a z-direction which is perpendicular with respect to the x-axis and to the y-axis;

a metallic layer which is attached to the dielectric layer in a planar manner; and

a component which is embedded in the dielectric layer and/or in a dielectric core-layer of the circuit board;

wherein the dielectric layer comprises a dielectric material which has an elastic modulus E in a range between 1 and 20 GPa and a coefficient of thermal expansion in a range between 0 and 17 ppm/K along the x-axis and along the y-axis;

wherein the dielectric material is a blend or a copolymer consisting of at least one first material with a first elastic modulus E and a first coefficient of thermal expansion and a second material with a second elastic modulus E and a second coefficient of thermal expansion;

wherein the first elastic modulus is larger than the second elastic modulus;

wherein the first coefficient of thermal expansion is smaller than the second coefficient of thermal expansion; and

wherein the second material comprises a thermally curable resin which is connected with a softening substance.

2. The circuit board of claim 1, further comprising at least one of the following features:

wherein the first material comprises a first glass transition temperature and the second material comprises a second glass transition temperature,

wherein the first glass transition temperature is larger than the second glass transition temperature,

wherein the first material comprises a resin and a hard filler which is contained therein.

3. The circuit board of claim 1,

wherein the value for the elastic modulus E is in a range between 2 and 7 GPa.

4. The circuit board of claim 1,

wherein the coefficient of thermal expansion is in a range between 3 and 10 ppm/K.

5. The circuit board of claim 1, further comprising:

wherein the dielectric core-layer is attached to the metallic layer and/or to the dielectric layer in a planar manner;

wherein the component is embedded in the dielectric core-layer and the dielectric layer is arranged above or below the dielectric core-layer and the embedded component.

6. The circuit board of claim 1,

wherein the component is embedded in the dielectric layer.

7. The circuit board of claim 1, further comprising at least one of the following features:

wherein the dielectric layer is a dielectric prepreg-layer and/or the dielectric material is a dielectric prepreg-material,

wherein the entire thickness of the layer composite is smaller than approximately 200 μ

m.

8. The circuit board of claim 1, which further comprises an asymmetric build-up with respect to a plane of the embedded component along an axis, wherein

the plane is oriented in parallel with respect to the planar surface of the dielectric layer,

the plane intersects the embedded component in the center, and

the axis is perpendicular with respect to this plane.

9. The circuit board of claim 5,

wherein the component is adhered in the dielectric core-layer.

10. The circuit board of claim 5,

wherein the dielectric core-layer comprises a dielectric core-material which has a coefficient of thermal expansion of 0 to 11 ppm/K along the x-axis and along the y-axis.

11. A method of manufacturing a circuit board, the method, comprising:

providing a dielectric layer which comprises a planar extension in parallel with respect to an xy-plane which is spanned by an x-axis and a y-axis perpendicular thereto, and comprises a layer thickness along a z-direction which is perpendicular with respect to the x-axis and to the y-axis; and

embedding a component in the dielectric layer and/or in a dielectric core-layer of the circuit board, wherein the dielectric core-layer is attached to the dielectric layer;

wherein the dielectric layer comprises a dielectric material which has an elastic modulus E in a range between 1 and 20 GPa and has a coefficient of thermal expansion in a range between 0 and 17 ppm/K along the x-axis and along the y-axis;

wherein the dielectric material is a blend or a copolymer consisting of at least one first material with a first elastic modulus E and a first coefficient of thermal expansion and a second material with a second elastic modulus E and a second coefficient of thermal expansion;

wherein the first elastic modulus is larger than the second elastic modulus;

wherein the first coefficient of thermal expansion is smaller than the second coefficient of thermal expansion; and

wherein the second material comprises a thermally curable resin which is connected with a softening substance.

12. The method of claim 11, further comprising:

forming a recess in the dielectric layer and/or in the dielectric core-layer;

wherein embedding the component comprises;

inserting the component in the recess.

13. The method of claim 11, further comprising at least one of the following features:

wherein embedding the component further comprises;

inserting an adhesive material in the recess;

wherein the recess is larger than the component, such that after an inserting of the component in the recess, a hollow remains.

14. The method of claim 11, further comprising:

if the component is embedded in the dielectric layer,

applying a further dielectric layer on the dielectric layer and the component, wherein the further dielectric layer has the same properties as the dielectric layer; and

if the component is embedded in the dielectric core-layer,

applying the dielectric layer on the dielectric core-layer and the component.

15. The method of claim 11, further comprising at least one of:

forming a metallic layer at the dielectric layer,

pressing all layers of the circuit board.

16. A method of manufacturing two processed circuit boards, the method, comprising:

building up a layer composite comprising

a first circuit board,

a second circuit board, and

a release layer which is arranged between the first circuit board and the second circuit board;

wherein the first and second circuit boards are arranged with a dielectric layer which includes

a planar extension in parallel with respect to an xy-plane which is spanned by an x-axis and a y-axis perpendicular thereto,

a layer thickness along a z-direction which is perpendicular with respect to the x-axis and to the y-axis;

a metallic layer which is attached to the dielectric layer in a planar manner; and

a component which is embedded in the dielectric layer and/or in a dielectric core-layer of the circuit board;

wherein the dielectric layer comprises a dielectric material which has an elastic modulus E in a range between 1 and 20 GPa and a coefficient of thermal expansion in a range between 0 and 17 ppm/K along the x-axis and along the y-axis; and

wherein the dielectric material is a blend or a copolymer consisting of at least one first material with a first elastic modulus E and a first coefficient of thermal expansion and a second material with a second elastic modulus E and a second coefficient of thermal expansion;

wherein the first elastic modulus is larger than the second elastic modulus;

wherein the first coefficient of thermal expansion is smaller than the second coefficient of thermal expansion;

wherein the second material comprises a thermally curable resin which is connected with a softening substance;

wherein the dielectric layer is a dielectric prepreg-layer and/or the dielectric material is a dielectric prepreg-material;

wherein the entire thickness of the layer composite is smaller than approximately 200 μ

m;

processing the entire layer composite; and

separating the layer composite at the release layer, such that a first processed circuit board and a second processed circuit board with respectively one asymmetric layer composite are generated.

17. The method of claim 16, further comprising at least one of the following features:

wherein the built up layer composite comprises a symmetry plane along the z-axis, which is oriented in parallel with respect to the xy-plane,

wherein the release layer comprises a printable adhesion reducing material and wherein the method further comprises

printing the adhesion reducing material on at least a subregion of the first circuit board or on at least a subregion of the second circuit board.