Analog front-end circuitry for biphasic stimulus signal delivery finding use in neural stimulation

• US 10,307,594 B2
• Filed: 06/17/2016
• Issued: 06/04/2019
• Est. Priority Date: 06/17/2015
• Status: Active Grant

• Current Assignee: University of Washington
• Original Assignee: University of Washington
• Inventors: Pepin, Eric, Rudell, Jacques Christophe
• Primary Examiner(s): Fairchild, Mallika D
• Application Number:
  US15/186,170
• Publication Number:
  US 20160367813A1
• Time in Patent Office: 1,082 Days
• CPC Class Codes: A61N 1/0529 Electrodes for brain stimulation
• CPC Class Codes: A61N 1/0551 Spinal or peripheral nerve electrodes
• CPC Class Codes: A61N 1/36125 Details of circuitry or electric components
• CPC Class Codes: A61N 1/36139 with automatic adjustment
• CPC Class Codes: A61N 1/36157 Current A61N1/3616 takes precedence
• CPC Class Codes: A61N 1/37205 Microstimulators, e.g. implantable through a cannula
• CPC Class Codes: A61N 1/37211 Means for communicating with stimulators

Abstract

Front-end analog circuitry is described based on a sink-regulated H-bridge topology for delivery of biphasic stimulus signals that may be useful in neurostimulation. Stimulus current may be supplied using fully-integrated dynamic voltage supplies (DVSs), which may be controlled in closed-loop to have an output voltage approximately equal to the voltage of the electrode each supplies stimulus to. The stimulus waveform may be regulated by a single, low-voltage current-digital-to-analog converter (current-DAC), which can safely interface with the electrodes (which may be at high voltages) via high-voltage adapter (HVA) circuits. Example analog front-end circuitry may utilize the balancing stimulus current to discharge the electrode-tissue interface impedance (Z_E). In some examples, only after full (or sufficient) Z_E discharge has been detected is a DVS used to supply the remaining balancing stimulus.

Claims

1. Analog front-end circuitry comprising:

a first current driver circuit comprising a first switched-capacitor power supply configured to produce a first high voltage;

a second current driver circuit comprising a second switched-capacitor power supply configured to produce a second high voltage; and

a first switch between the first current driver circuit and a first node;

a second switch between the second current driver circuit and a second node;

a first high voltage adapter circuit coupled to the first node;

a second high voltage adapter circuit coupled to the second node;

a current digital-to-analog converter (DAC);

a third switch between the first high voltage adapter circuit and the current digital-to-analog converter;

a fourth switch between the second high voltage adapter circuit and the current digital-to-analog converter;

a fifth switch between the first high voltage adapter circuit and a reference voltage;

a sixth switch between the second high voltage adapter circuit and the reference voltage;

wherein the first current driver circuit and the second current driver circuit are configured to control at least some of the first, second, third, fourth, fifth, and sixth switches to provide a biphasic voltage signal between the first and second node.

2. The circuitry of claim 1 further comprising:

a seventh switch between the first high voltage adapter circuit and a voltage comparator; and

an eight switch between the second high voltage adapter circuit and the voltage comparator;

wherein the first current driver circuit and the second current driver circuit are configured to control at least some of the first, second, third, fourth, fifth, sixth, seventh, and eighth switches to provide the biphasic voltage signal.

3. The circuitry of claim 2, wherein the first current driver circuit and the second current driver circuit are together configured to control the first, second, third, fourth, fifth, sixth, seventh, and eighth switches to:

in a first state, provide the reference voltage at both the first and second nodes by disconnecting the first and second nodes from the first and second high voltages;

in a second state, connect the second current driver circuit to the first node to provide the second high voltage to the first node, connect the second high voltage adapter circuit to the current DAC, and disconnect the first high voltage adapter circuit from the current DAC and the reference voltage;

in a third state, disconnect the first node from the second current driver circuit, connect the second high voltage adapter circuit to the reference voltage, and connect the first high voltage adapter circuit to the voltage comparator;

in a fourth state, connect the first high voltage adapter circuit to the reference voltage, connect the second high voltage adapter circuit to the current DAC and the voltage comparator;

in a fifth state, connect the first current driver circuit to the second node to provide the first high voltage to the second node, connect the first high voltage adapter circuit to the current DAC; and

in a sixth state, disconnect the second node from the first current driver circuit, connect the first high voltage adapter circuit to the reference voltage.

4. The circuitry of claim 3, wherein the first current driver comprises a first controller configured to cycle through the first, second, third, fourth, fifth, and sixth states, and wherein the second current driver comprises a second controller configured to cycle through the first, second, third, fourth, fifth, and sixth states.

5. The circuitry of claim 1, wherein the first node is configured to couple to a stimulus electrode, and wherein the second node is configured to couple to a reference electrode.

6. The circuitry of claim 1, wherein the first switched-capacitor power supply and the second switched-capacitor power supply comprise transistors configured for operation with a first power supply voltage and wherein the first and second high voltages are at least twice the first power supply voltage.

7. The circuitry of claim 1, wherein the first current driver circuit and the second current driver circuit each comprise a clocked controller.

8. The circuitry of claim 1, wherein the first current driver circuit and the second current driver circuit each are operable in two modes including a first mode configured to provide operation during supply of the first or second high voltages and a second mode configured to track voltage of the first or second nodes during discharge.

9. Circuitry for delivering a biphasic stimulus signal, the circuitry comprising:

a current source and a plurality of high voltage adapter circuits arranged in an H-bridge topology;

a plurality of dynamic voltage sources configured to provide voltages for the biphasic stimulus signal, wherein the plurality of states includes a first state providing a negative stimulus, a second state providing an interphase delay, a third state providing a positive stimulus through impedance discharge, and a fourth state providing a positive stimulus through current driver circuitry; and

a controller configured to cycle the H-bridge topology and plurality of dynamic voltage sources through a plurality of states to provide the biphasic stimulus signal.

10. The circuitry of claim 9, wherein the plurality of states further includes an idle state and an impedance discharge state.

11. The circuitry of claim 9, wherein the circuitry further comprises switches and wherein the controller is configured to open and close the switches to cycle through the plurality of states.

12. The circuitry of claim 9, wherein the controller comprises a digital state machine.