Facilitating recording a trace file of code execution using index bits in a processor cache

• US 10,310,963 B2
• Filed: 05/24/2017
• Issued: 06/04/2019
• Est. Priority Date: 10/20/2016
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Mola, Jordi
• Primary Examiner(s): Perez-Velez, Rocio Del Mar
• Assistant Examiner(s): Otto, Alan
• Application Number:
  US15/604,334
• Publication Number:
  US 20180113788A1
• Time in Patent Office: 741 Days
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 2212/453 Microcode or microprogram

Abstract

Facilitating recording a trace file of code execution using a processor cache. A method includes identifying an operation by a processing unit on a line of the cache. Based on identifying the operation, index bits for the cache line are set. Setting the index bits includes one of: (i) setting the bits to a reserved value when the operation is a write operation and tracing is disabled, (i) setting the bits to an index of the processing unit when the operation is a write operation and the bits are already set to a value other than the index of the processing unit, or (iii) setting the bits to the index of the processing unit when the operation is a read operation that is consumed by the processing unit and the bits are already set to a value other than the index of the processing unit.

Claims

1. A computing device for facilitating recording a trace of code execution using a processor cache, the computing device comprising:

a plurality of processing units;

the processor cache, which is shared by the plurality of processing units and which is configured to cache data from a memory device, the processor cache including;

a plurality of cache lines that each comprise at least (i) an address portion for storing a memory address of the memory device, and (ii) a value portion for storing a value associated with the memory address; and

different pluralities of accounting bits, each plurality of accounting bits being associated with a different cache line of the plurality of cache lines; and

stored control logic that is configured to use the different pluralities of accounting bits to indicate, for each cache line at least one of;

an index to one of the plurality of processing units for which a trace file logs a current value stored in the value portion of the cache line;

or

an indicator that the trace file does not log the value portion of the cache line for any processing unit.

2. The computing device of claim 1, wherein each cache line also comprises its corresponding plurality of accounting bits.

3. The computing device of claim 1, wherein the pluralities of accounting bits are stored in one or more reserved cache lines of the processor cache, each reserved cache line including accounting bits two or more of the plurality of cache lines.

4. The computing device of claim 1, wherein the stored control logic indicates whether or not a trace stream for a particular processing unit logs at least the current value stored in the value portion of a particular cache line by setting the accounting bits associated with the particular cache line to an index of the particular processing unit, to indicate that the trace stream for the particular processing unit does log at least the current value stored in the value portion of the particular cache line.

5. The computing device of claim 1, wherein the stored control logic is configured to detect a read operation on a particular cache line that is consumed by a particular processing unit, and to perform at least the following as a result of the read operation:

determine that the accounting bits associated with the particular cache line are set to a value other than an index of the particular processing unit; and

based on the accounting bits being set to a value other than an index of the particular processing unit;

log at least a value stored in the value portion of the particular cache line into the trace file on behalf of the particular processing unit; and

set the accounting bits associated with the particular cache line to the index of the particular processing unit.

6. The computing device of claim 1, wherein the stored control logic is configured to detect a write operation by a particular processing unit on a particular cache line, and to perform one of the following as a result of the write operation:

based at least determining that tracing is disabled, set the accounting bits associated with the particular cache line to a reserved value;

or

based at least on determining that the accounting bits associated with the particular cache line are set to a value other than an index of the particular processing unit, set the accounting bits associated with the particular cache line to the index of the particular processing unit.

7. The computing device of claim 1, wherein the pluralities of accounting bits also include reference bits for referencing a value already saved on the trace file.