Method and apparatus for processing memory page in memory

• US 10,310,971 B2
• Filed: 07/17/2017
• Issued: 06/04/2019
• Est. Priority Date: 01/15/2015
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Liu, Duo, Shao, Zili, Long, Linbo
• Primary Examiner(s): Bragdon, Reginald G
• Assistant Examiner(s): Vo, Thanh D
• Application Number:
  US15/651,862
• Publication Number:
  US 20170315931A1
• Time in Patent Office: 687 Days
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

A method for processing a memory page in memory, where the memory page in the memory includes an idle single-level cell (SLC) memory page, an active SLC memory page, an inactive SLC memory page, and a multi-level cell (MLC) memory page, and when a quantity of idle SLC memory pages of any virtual machine (VM) is less than a specified threshold, the processing method includes converting one idle SLC memory page to two MLC memory pages, copying data in two inactive SLC memory pages to the two converted MLC memory pages, and releasing storage space of the two inactive SLC memory pages to obtain two idle SLC memory pages.

Claims

1. A method for processing a memory page in memory, wherein the memory page in the memory comprises an idle single-level cell (SLC) memory page, an active SLC memory page, an inactive SLC memory page, and a multi-level cell (MLC) memory page, wherein the idle SLC memory page has no data, wherein data stored in the active SLC memory page is data accessed within a specified time period, wherein data stored in the inactive SLC memory page and the MLC memory page is data not accessed within the specified time period, and wherein the processing method comprises:

converting one idle SLC memory page to two MLC memory pages when a quantity of idle SLC memory pages in any virtual machine (VM) is less than a specified threshold;

copying data in two inactive SLC memory pages to the two converted MLC memory pages; and

releasing storage space of the two inactive SLC memory pages to obtain two idle SLC memory pages.

2. The method according to claim 1, wherein a higher memory access frequency or higher memory usage indicates a shorter specified time period, or wherein the higher memory access frequency and the higher memory usage indicate the shorter specified time period.

3. The method according to claim 1, wherein a smaller specified threshold indicates higher memory access performance and a higher probability of generating a page fault.

4. The method according to claim 1, wherein after determining that the quantity of idle SLC memory pages in the any VM is less than the specified threshold and when a quantity of current inactive SLC memory pages is less than 2, the method further comprises:

writing the data in the two MLC memory pages back to an external storage; and

converting the two MLC memory pages to one idle SLC memory page.

5. The method according to claim 4, wherein after determining that the quantity of idle SLC memory pages in the any VM is less than the specified threshold, the method further comprises obtaining an idle memory page of another VM for the any VM when the quantity of current inactive SLC memory pages is less than 2 and a quantity of current MLC memory pages is less than 2.

6. The method according to claim 1, further comprising:

allocating an idle SLC memory page for a memory allocation request after the memory allocation request is received; and

re-identifying the idle SLC memory page as an active SLC memory page.

7. The method according to claim 6, wherein re-identifying the idle SLC memory page as the active SLC memory page comprises transferring an address of the idle SLC memory page from an established idle SLC memory page linked list to an established active SLC memory page linked list.

8. The method according to claim 1, further comprising re-identifying an inactive SLC memory page as an active SLC memory page after an access request for the inactive SLC memory page is received.

9. The method according to claim 8, wherein re-identifying the inactive SLC memory page as the active SLC memory page comprises transferring an address of the inactive SLC memory page from an established inactive SLC memory page linked list to an established active SLC memory page linked list.

10. The method according to claim 1, further comprising re-identifying an active SLC memory page as an inactive SLC memory page when no access request for the active SLC memory page is received within the specified time period.

11. The method according to claim 10, wherein re-identifying the active SLC memory page as the inactive SLC memory page comprises transferring an address of the active SLC memory page from an established active SLC memory page linked list to an established inactive SLC memory page linked list.

12. An apparatus for processing a memory page in memory, wherein the memory page in the memory comprises an idle single-level cell (SLC) memory page, an active SLC memory page, an inactive SLC memory page, and a multi-level cell (MLC) memory page, wherein the idle SLC memory page has no data, wherein data stored in the active SLC memory page is data accessed within a specified time period, wherein data stored in the inactive SLC memory page and the MLC memory page is data not accessed within the specified time period, and wherein the apparatus comprises:

a storage comprising instructions; and

a processor coupled to the storage, wherein the instructions cause the processor to be configured to;

convert one idle SLC memory page to two MLC memory pages when a quantity of idle SLC memory pages in any virtual machine (VM) is less than a specified threshold;

copy data in two inactive SLC memory pages to the two converted MLC memory pages; and

release storage space of the two inactive SLC memory pages to obtain two idle SLC memory pages.

13. The apparatus according to claim 12, wherein a higher memory access frequency or higher memory usage indicates a shorter specified time period, or wherein the higher memory access frequency and the higher memory usage indicate the shorter specified time period.

14. The apparatus according to claim 12, wherein a smaller specified threshold indicates higher memory access performance and a higher probability of generating a page fault.

15. The apparatus according to claim 14, wherein after determining that the quantity of idle SLC memory pages in the any VM is less than the specified threshold, and when a quantity of current inactive SLC memory pages is less than 2, the instructions further cause the processor to be configured to:

write the data in the two MLC memory pages back to an external storage; and

convert the two MLC memory pages to one idle SLC memory page.

16. The apparatus according to claim 15, wherein after determining the quantity of idle SLC memory pages in the any VM is less than the specified threshold, and when the quantity of current inactive SLC memory pages is less than 2 and a quantity of current MLC memory pages is less than 2, the instructions further cause the processor to be configured to obtain an idle memory page of another VM for the any VM.

17. The apparatus according to claim 12, wherein the instructions further cause the processor to be configured to:

allocate an idle SLC memory page for a memory allocation request after the memory allocation request is received; and

re-identify the idle SLC memory page as an active SLC memory page.

18. The apparatus according to claim 17, wherein the instructions further cause the processor to be configured to transfer an address of the idle SLC memory page from an established idle SLC memory page linked list to an established active SLC memory page linked list.

19. The apparatus according to claim 12, wherein the instructions further cause the processor to be configured to re-identify an inactive SLC memory page as an active SLC memory page after an access request for the inactive SLC memory page is received.

20. The apparatus according to claim 19, wherein the instructions further cause the processor to be configured to transfer an address of the inactive SLC memory page from an established inactive SLC memory page linked list to an established active SLC memory page linked list.

21. The apparatus according to claim 12, wherein when no access request for an active SLC memory page is received within the specified time period, the instructions further cause the processor to be configured to re-identify the active SLC memory page as an inactive SLC memory page.

22. The apparatus according to claim 21, wherein the instructions further cause the processor to be configured to transfer an address of the active SLC memory page from an established active SLC memory page linked list to an established inactive SLC memory page linked list.