Direct memory access with filtering

• US 10,310,998 B2
• Filed: 06/30/2015
• Issued: 06/04/2019
• Est. Priority Date: 06/30/2015
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Haraden, Ryan, Shearer, Robert, Tubbs, Matthew, Muff, Adam, Gupta, Ashish
• Primary Examiner(s): Lee, Chun Kuan
• Application Number:
  US14/788,317
• Publication Number:
  US 20170004092A1
• Time in Patent Office: 1,435 Days
• Field of Search: 710308
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: H04N 23/81 for suppressing or minimising disturbance in the image signal generation
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods, apparatus, and computer-readable storage media are disclosed for applying filtering operations to data transferred as part of a direct memory access (DMA) operation. In one example of the disclosed technology, a system includes a processor, memory, and a direct memory access (DMA) engine coupled to the memory for reading a set of data from a selected range of read memory addresses for the memory without using the processor. A line buffer coupled to the DMA engine is configured to receive DMA read data and temporarily store a portion, but not all of the data set being read by the DMA engine in a line buffer. A digital filter is configured to apply a filtering operation to a windowed subset of the buffered portion of the data set, producing filtered data that is stored to a selected range of write memory addresses for the memory, without using the processor.

Claims

1. A system, comprising:

memory;

a direct memory access (DMA) engine coupled to the memory, the DMA engine including a DMA read circuit and a DMA write circuit, the DMA read circuit being configured for reading a set of data from a selected range of read memory addresses for the memory;

a filter having a window height and being configured to apply a filtering operation to a window-height subset of a buffered portion of the data set, producing filtered data, the filter being further configured to provide substitute pixels for one or more edge pixels of the set of data prior to the filtering operation;

a line buffer coupled to the DMA engine and configured to receive the read data and to temporarily store a portion but not all of the data set being read by the DMA engine as the window-height subset of the buffered portion of the data set, the line buffer including at least one more row of data than the window height; and

wherein the DMA write circuit stores the filtered data to a selected range of write memory addresses of the memory.

2. The system of claim 1, further comprising a processor having a plurality of processor registers, and wherein the DMA read circuit is configured to read the data set directly from memory without using the processor registers, and wherein the DMA write circuit is configured to write directly to the memory without using the processor registers.

3. The system of claim 2, wherein the processor and the DMA engine are coupled to the memory with a multi-drop bus or a plurality of point-to-point busses.

4. The system of claim 2, further comprising an image sensor configured to detect an image and store image data corresponding to the image in the memory.

5. The system of claim 1, wherein the filter is a spatial domain filter, the filter being further configured to apply at least one or more of the following filtering operations to the subset of the buffered portion of the data set:

a bilateral filter, a joint bilateral filter, a convolution filter, or a finite impulse response filter.

6. The system of claim 1, wherein the filter is further configured to apply the filtering operation to a 5×

5 or a 3×

3 pixel subset of the buffered portion of the data set.

7. The system of claim 1, wherein the filter is further configured to skip filtering for one or more edge pixels of the set of data.

8. The system of claim 1, wherein the data set comprises two or more tile regions, and wherein the filter is further configured to skip filtering for one or more edge pixels near a boundary of two of the two or more tile regions.

9. A method comprising:

with a line buffer, receiving data from a direct memory access (DMA) read circuit coupled to a memory for a selected range of read memory addresses for the memory and temporarily storing a portion but not all of the received data as a window-height subset of the received data;

providing substitute pixels for at least one edge pixel of the window-height subset of data;

filtering the window-height subset with the substitute pixels, producing filtered data; and

storing the filtered data to a range of write memory addresses via a DMA write circuit.

10. The method of claim 9, wherein the memory is coupled to a processor having a plurality of processor registers, and wherein the DMA read circuit is configured to read the data directly from the memory without using the processor registers, and wherein the DMA write circuit is configured to write directly to the memory without using the processor registers.

11. The method of claim 9, further comprising using an image sensor to detect an image and store image data corresponding to the image in the memory.

12. The method of claim 9, wherein the filtering comprises spatial domain filtering, the filtering further comprising applying at least one of the following operations to the window-height subset:

a bilateral filter, a joint bilateral filter, a convolution filter, or a finite impulse response filter.

13. The method of claim 9, wherein the filtering comprises applying a filtering operation to a 5×

5 or a 3×

3 pixel subset of the window-height subset.

14. The method of claim 9, wherein the data set comprises two or more tile regions, and wherein the filtering comprises performing skip filtering for one or more edge pixels near a boundary of two of the two or more tile regions.

15. An apparatus, comprising:

memory;

a direct memory access (DMA) engine coupled to the memory, the DMA engine including a DMA read circuit and a DMA write circuit, the DMA read circuit being configured to read a set of data from a selected range of read memory addresses for the memory;

a filter having a window height and being configured to apply a filtering operation to a window-height subset of a buffered portion of the data set, producing filtered data, the filter being further configured to copy pixel intensity values from neighboring pixels for one or more missing edge pixels of the set of data prior to the filtering operation;

a line buffer coupled to the DMA engine and configured to receive the read data and to temporarily store a portion but not all of the data set being read by the DMA engine as the window-height subset of the buffered portion of the data set, the line buffer including at least one more row of data than the window height; and

wherein the DMA write circuit stores the filtered data to a selected range of write memory addresses of the memory.

16. The apparatus of claim 15, further comprising an image sensor configured to detect an image and store image data corresponding to the image in the memory.

17. The apparatus of claim 15, wherein the filter is a spatial domain filter, the filter being further configured to apply at least one or more of the following filtering operations to the subset of the buffered portion of the data set:

a bilateral filter, a joint bilateral filter, a convolution filter, or a finite impulse response filter.

18. The apparatus of claim 15, wherein the filter is further configured to apply the filtering operation to a 5×

5 or a 3×

3 pixel subset of the buffered portion of the data set.

19. The apparatus of claim 15, wherein the data set comprises two or more tile regions, and wherein the filter is further configured to skip filtering for one or more edge pixels near a boundary of two of the two or more tile regions.

20. The apparatus of claim 15, wherein the filter is further configured to copy the pixel intensity values by combining two or more surrounding pixels.